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[PATCH v7 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR acces
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From: |
Anup Patel |
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Subject: |
[PATCH v7 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode |
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Date: |
Mon, 17 Jan 2022 18:58:04 +0530 |
From: Anup Patel <anup.patel@wdc.com>
We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.
Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index adb3d4381d..bee42b6073 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -182,7 +182,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
static RISCVException hmode32(CPURISCVState *env, int csrno)
{
if (riscv_cpu_mxl(env) != MXL_RV32) {
- if (riscv_cpu_virt_enabled(env)) {
+ if (!riscv_cpu_virt_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
} else {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
--
2.25.1
- [PATCH v7 05/23] target/riscv: Allow setting CPU feature from machine/device emulation, (continued)
- [PATCH v7 05/23] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2022/01/17
- [PATCH v7 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback, Anup Patel, 2022/01/17
- [PATCH v7 03/23] target/riscv: Implement hgeie and hgeip CSRs, Anup Patel, 2022/01/17
- [PATCH v7 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2022/01/17
- [PATCH v7 09/23] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2022/01/17
- [PATCH v7 15/23] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2022/01/17
- [PATCH v7 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode,
Anup Patel <=
- [PATCH v7 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2022/01/17
- [PATCH v7 14/23] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2022/01/17
- [PATCH v7 04/23] target/riscv: Improve delivery of guest external interrupts, Anup Patel, 2022/01/17
- [PATCH v7 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2022/01/17
- [PATCH v7 07/23] target/riscv: Add defines for AIA CSRs, Anup Patel, 2022/01/17
- [PATCH v7 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs, Anup Patel, 2022/01/17
- [PATCH v7 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Anup Patel, 2022/01/17
- [PATCH v7 16/23] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2022/01/17
- [PATCH v7 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation, Anup Patel, 2022/01/17