Re: [PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns

[Alistair Francis]

On Wed, Dec 29, 2021 at 12:39 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> All Zve* extensions support the vector configuration instructions.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 230c475d6c..c6280c7b0b 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -152,7 +152,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, 
> TCGv s2)
>      TCGv s1, dst;
>
>      if (!require_rvv(s) ||
> -        !(has_ext(s, RVV) || s->ext_zve64f)) {
> +        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
>          return false;
>      }
>
> @@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, 
> TCGv s2)
>      TCGv dst;
>
>      if (!require_rvv(s) ||
> -        !(has_ext(s, RVV) || s->ext_zve64f)) {
> +        !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
>          return false;
>      }
>
> --
> 2.31.1
>
>