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[PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration
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From: |
Alistair Francis |
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Subject: |
[PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns |
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Date: |
Fri, 21 Jan 2022 15:57:49 +1000 |
From: Frank Chang <frank.chang@sifive.com>
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 6c285c958b..5b47729a21 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -129,7 +129,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,
TCGv s2)
{
TCGv s1, dst;
- if (!require_rvv(s) || !has_ext(s, RVV)) {
+ if (!require_rvv(s) ||
+ !(has_ext(s, RVV) || s->ext_zve64f)) {
return false;
}
@@ -164,7 +165,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1,
TCGv s2)
{
TCGv dst;
- if (!require_rvv(s) || !has_ext(s, RVV)) {
+ if (!require_rvv(s) ||
+ !(has_ext(s, RVV) || s->ext_zve64f)) {
return false;
}
--
2.31.1
- [PULL 00/61] riscv-to-apply queue, Alistair Francis, 2022/01/21
- [PULL 01/61] hw: timer: ibex_timer: Fixup reading w/o register, Alistair Francis, 2022/01/21
- [PULL 02/61] riscv: opentitan: fixup plic stride len, Alistair Francis, 2022/01/21
- [PULL 03/61] hw: timer: ibex_timer: update/add reg address, Alistair Francis, 2022/01/21
- [PULL 04/61] update-linux-headers: Add asm-riscv/kvm.h, Alistair Francis, 2022/01/21
- [PULL 05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface, Alistair Francis, 2022/01/21
- [PULL 07/61] target/riscv: Implement kvm_arch_get_registers, Alistair Francis, 2022/01/21
- [PULL 10/61] target/riscv: Support setting external interrupt by KVM, Alistair Francis, 2022/01/21
- [PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns,
Alistair Francis <=
- [PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu, Alistair Francis, 2022/01/21
- [PULL 09/61] target/riscv: Support start kernel directly by KVM, Alistair Francis, 2022/01/21
- [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Alistair Francis, 2022/01/21
- [PULL 12/61] target/riscv: Add host cpu type, Alistair Francis, 2022/01/21
- [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer, Alistair Francis, 2022/01/21
- [PULL 08/61] target/riscv: Implement kvm_arch_put_registers, Alistair Francis, 2022/01/21
- [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing, Alistair Francis, 2022/01/21
- [PULL 15/61] target/riscv: Support virtual time context synchronization, Alistair Francis, 2022/01/21
- [PULL 16/61] target/riscv: enable riscv kvm accel, Alistair Francis, 2022/01/21
- [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers, Alistair Francis, 2022/01/21