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[PULL 16/61] target/riscv: enable riscv kvm accel
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From: |
Alistair Francis |
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Subject: |
[PULL 16/61] target/riscv: enable riscv kvm accel |
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Date: |
Fri, 21 Jan 2022 15:57:45 +1000 |
From: Yifei Jiang <jiangyifei@huawei.com>
Add riscv kvm support in meson.build file.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Message-id: 20220112081329.1835-14-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meson.build b/meson.build
index 333c61deba..833fd6bc4c 100644
--- a/meson.build
+++ b/meson.build
@@ -90,6 +90,8 @@ elif cpu in ['ppc', 'ppc64']
kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
elif cpu in ['mips', 'mips64']
kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu',
'mips64el-softmmu']
+elif cpu in ['riscv']
+ kvm_targets = ['riscv32-softmmu', 'riscv64-softmmu']
else
kvm_targets = []
endif
--
2.31.1
- [PULL 10/61] target/riscv: Support setting external interrupt by KVM, (continued)
- [PULL 10/61] target/riscv: Support setting external interrupt by KVM, Alistair Francis, 2022/01/21
- [PULL 20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, Alistair Francis, 2022/01/21
- [PULL 06/61] target/riscv: Implement function kvm_arch_init_vcpu, Alistair Francis, 2022/01/21
- [PULL 09/61] target/riscv: Support start kernel directly by KVM, Alistair Francis, 2022/01/21
- [PULL 11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Alistair Francis, 2022/01/21
- [PULL 12/61] target/riscv: Add host cpu type, Alistair Francis, 2022/01/21
- [PULL 13/61] target/riscv: Add kvm_riscv_get/put_regs_timer, Alistair Francis, 2022/01/21
- [PULL 08/61] target/riscv: Implement kvm_arch_put_registers, Alistair Francis, 2022/01/21
- [PULL 14/61] target/riscv: Implement virtual time adjusting with vm state changing, Alistair Francis, 2022/01/21
- [PULL 15/61] target/riscv: Support virtual time context synchronization, Alistair Francis, 2022/01/21
- [PULL 16/61] target/riscv: enable riscv kvm accel,
Alistair Francis <=
- [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers, Alistair Francis, 2022/01/21
- [PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment, Alistair Francis, 2022/01/21
- [PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, Alistair Francis, 2022/01/21
- [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, Alistair Francis, 2022/01/21
- [PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, Alistair Francis, 2022/01/21
- [PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, Alistair Francis, 2022/01/21
- [PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, Alistair Francis, 2022/01/21
- [PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, Alistair Francis, 2022/01/21
- [PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, Alistair Francis, 2022/01/21
- [PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, Alistair Francis, 2022/01/21