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[PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width
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From: |
Alistair Francis |
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Subject: |
[PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns |
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Date: |
Fri, 21 Jan 2022 15:57:54 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Vector single-width floating-point reduction operations for EEW=32 are
supported for Zve64f extension.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-8-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 56246a5d88..08f25e3ce4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2937,7 +2937,8 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
static bool freduction_check(DisasContext *s, arg_rmrr *a)
{
return reduction_check(s, a) &&
- require_rvf(s);
+ require_rvf(s) &&
+ require_zve64f(s);
}
GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
--
2.31.1
- [PULL 15/61] target/riscv: Support virtual time context synchronization, (continued)
- [PULL 15/61] target/riscv: Support virtual time context synchronization, Alistair Francis, 2022/01/21
- [PULL 16/61] target/riscv: enable riscv kvm accel, Alistair Francis, 2022/01/21
- [PULL 17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers, Alistair Francis, 2022/01/21
- [PULL 18/61] softmmu/device_tree: Remove redundant pointer assignment, Alistair Francis, 2022/01/21
- [PULL 21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, Alistair Francis, 2022/01/21
- [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, Alistair Francis, 2022/01/21
- [PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, Alistair Francis, 2022/01/21
- [PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, Alistair Francis, 2022/01/21
- [PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, Alistair Francis, 2022/01/21
- [PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, Alistair Francis, 2022/01/21
- [PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns,
Alistair Francis <=
- [PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, Alistair Francis, 2022/01/21
- [PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, Alistair Francis, 2022/01/21
- [PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns, Alistair Francis, 2022/01/21
- [PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, Alistair Francis, 2022/01/21
- [PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns, Alistair Francis, 2022/01/21
- [PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns, Alistair Francis, 2022/01/21
- [PULL 49/61] target/riscv: Create current pm fields in env, Alistair Francis, 2022/01/21
- [PULL 50/61] target/riscv: Alloc tcg global for cur_pm[mask|base], Alistair Francis, 2022/01/21
- [PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on, Alistair Francis, 2022/01/21
- [PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns, Alistair Francis, 2022/01/21