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[PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration
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From: |
Alistair Francis |
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Subject: |
[PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns |
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Date: |
Fri, 21 Jan 2022 15:57:59 +1000 |
From: Frank Chang <frank.chang@sifive.com>
All Zve* extensions support the vector configuration instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-13-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 9fa3862620..fd6e74c232 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -152,7 +152,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,
TCGv s2)
TCGv s1, dst;
if (!require_rvv(s) ||
- !(has_ext(s, RVV) || s->ext_zve64f)) {
+ !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
return false;
}
@@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1,
TCGv s2)
TCGv dst;
if (!require_rvv(s) ||
- !(has_ext(s, RVV) || s->ext_zve64f)) {
+ !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) {
return false;
}
--
2.31.1
- [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, (continued)
- [PULL 22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, Alistair Francis, 2022/01/21
- [PULL 23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, Alistair Francis, 2022/01/21
- [PULL 29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, Alistair Francis, 2022/01/21
- [PULL 19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, Alistair Francis, 2022/01/21
- [PULL 24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, Alistair Francis, 2022/01/21
- [PULL 25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, Alistair Francis, 2022/01/21
- [PULL 26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, Alistair Francis, 2022/01/21
- [PULL 28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, Alistair Francis, 2022/01/21
- [PULL 31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns, Alistair Francis, 2022/01/21
- [PULL 27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, Alistair Francis, 2022/01/21
- [PULL 30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns,
Alistair Francis <=
- [PULL 32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns, Alistair Francis, 2022/01/21
- [PULL 49/61] target/riscv: Create current pm fields in env, Alistair Francis, 2022/01/21
- [PULL 50/61] target/riscv: Alloc tcg global for cur_pm[mask|base], Alistair Francis, 2022/01/21
- [PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on, Alistair Francis, 2022/01/21
- [PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns, Alistair Francis, 2022/01/21
- [PULL 34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns, Alistair Francis, 2022/01/21
- [PULL 51/61] target/riscv: Calculate address according to XLEN, Alistair Francis, 2022/01/21
- [PULL 38/61] roms/opensbi: Remove ELF images, Alistair Francis, 2022/01/21
- [PULL 52/61] target/riscv: Split pm_enabled into mask and base, Alistair Francis, 2022/01/21
- [PULL 39/61] target/riscv: Adjust pmpcfg access with mxl, Alistair Francis, 2022/01/21