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[PULL 41/61] target/riscv: Sign extend link reg for jal and jalr
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From: |
Alistair Francis |
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Subject: |
[PULL 41/61] target/riscv: Sign extend link reg for jal and jalr |
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Date: |
Fri, 21 Jan 2022 15:58:10 +1000 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-4-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 4 +---
target/riscv/insn_trans/trans_rvi.c.inc | 4 +---
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 330904265e..30c0e28778 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -369,10 +369,8 @@ static void gen_jal(DisasContext *ctx, int rd,
target_ulong imm)
return;
}
}
- if (rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
- }
+ gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety
*/
ctx->base.is_jmp = DISAS_NORETURN;
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 3a0ae28fef..b9ba57f266 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -68,9 +68,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
tcg_temp_free(t0);
}
- if (a->rd != 0) {
- tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
- }
+ gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
tcg_gen_lookup_and_goto_ptr();
if (misaligned) {
--
2.31.1
- [PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on, (continued)
- [PULL 35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on, Alistair Francis, 2022/01/21
- [PULL 33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns, Alistair Francis, 2022/01/21
- [PULL 34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns, Alistair Francis, 2022/01/21
- [PULL 51/61] target/riscv: Calculate address according to XLEN, Alistair Francis, 2022/01/21
- [PULL 38/61] roms/opensbi: Remove ELF images, Alistair Francis, 2022/01/21
- [PULL 52/61] target/riscv: Split pm_enabled into mask and base, Alistair Francis, 2022/01/21
- [PULL 39/61] target/riscv: Adjust pmpcfg access with mxl, Alistair Francis, 2022/01/21
- [PULL 36/61] hw/riscv: spike: Allow using binary firmware as bios, Alistair Francis, 2022/01/21
- [PULL 37/61] hw/riscv: Remove macros for ELF BIOS image names, Alistair Francis, 2022/01/21
- [PULL 40/61] target/riscv: Don't save pc when exception return, Alistair Francis, 2022/01/21
- [PULL 41/61] target/riscv: Sign extend link reg for jal and jalr,
Alistair Francis <=
- [PULL 43/61] target/riscv: Create xl field in env, Alistair Francis, 2022/01/21
- [PULL 42/61] target/riscv: Sign extend pc for different XLEN, Alistair Francis, 2022/01/21
- [PULL 44/61] target/riscv: Ignore the pc bits above XLEN, Alistair Francis, 2022/01/21
- [PULL 45/61] target/riscv: Extend pc for runtime pc write, Alistair Francis, 2022/01/21
- [PULL 54/61] target/riscv: Adjust vsetvl according to XLEN, Alistair Francis, 2022/01/21
- [PULL 55/61] target/riscv: Remove VILL field in VTYPE, Alistair Francis, 2022/01/21
- [PULL 58/61] target/riscv: Adjust scalar reg in vector with XLEN, Alistair Francis, 2022/01/21
- [PULL 46/61] target/riscv: Use gdb xml according to max mxlen, Alistair Francis, 2022/01/21
- [PULL 47/61] target/riscv: Relax debug check for pm write, Alistair Francis, 2022/01/21
- [PULL 56/61] target/riscv: Fix check range for first fault only, Alistair Francis, 2022/01/21