[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 28/42] hw/cxl/component: Add utils for interleave parameter en
|
From: |
Jonathan Cameron |
|
Subject: |
[PATCH v4 28/42] hw/cxl/component: Add utils for interleave parameter encoding/decoding |
|
Date: |
Mon, 24 Jan 2022 17:16:51 +0000 |
From: Jonathan Cameron <jonathan.cameron@huawei.com>
Both registers and the CFMWS entries in CDAT use simple encodings
for the number of interleave ways and the interleave granularity.
Introduce simple conversion functions to/from the unencoded
number / size. So far the iw decode has not been needed so is
it not implemented.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/cxl/cxl-component-utils.c | 34 ++++++++++++++++++++++++++++++++++
include/hw/cxl/cxl_component.h | 8 ++++++++
2 files changed, 42 insertions(+)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 5007b29ebb..be2c5599d6 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -9,6 +9,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
+#include "qapi/error.h"
#include "hw/pci/pci.h"
#include "hw/cxl/cxl.h"
@@ -210,3 +211,36 @@ void cxl_component_create_dvsec(CXLComponentState *cxl,
uint16_t length,
range_init_nofail(&cxl->dvsecs[type], cxl->dvsec_offset, length);
cxl->dvsec_offset += length;
}
+
+uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
+{
+ switch (iw) {
+ case 1: return 0x0;
+ case 2: return 0x1;
+ case 4: return 0x2;
+ case 8: return 0x3;
+ case 16: return 0x4;
+ case 3: return 0x8;
+ case 6: return 0x9;
+ case 12: return 0xa;
+ default:
+ error_setg(errp, "Interleave ways: %d not supported", iw);
+ return 0;
+ }
+}
+
+uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp)
+{
+ switch (gran) {
+ case 256: return 0;
+ case 512: return 1;
+ case 1024: return 2;
+ case 2048: return 3;
+ case 4096: return 4;
+ case 8192: return 5;
+ case 16384: return 6;
+ default:
+ error_setg(errp, "Interleave granularity: %lu invalid", gran);
+ return 0;
+ }
+}
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index 30e576351d..d30c3f4716 100644
--- a/include/hw/cxl/cxl_component.h
+++ b/include/hw/cxl/cxl_component.h
@@ -193,4 +193,12 @@ void cxl_component_register_init_common(uint32_t
*reg_state,
void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, uint16_t length,
uint16_t type, uint8_t rev, uint8_t *body);
+uint8_t cxl_interleave_ways_enc(int iw, Error **errp);
+uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp);
+
+static inline hwaddr cxl_decode_ig(int ig)
+{
+ return 1 << (ig + 8);
+}
+
#endif
--
2.32.0
- [PATCH v4 19/42] hw/cxl/rp: Add a root port, (continued)
- [PATCH v4 19/42] hw/cxl/rp: Add a root port, Jonathan Cameron, 2022/01/24
- [PATCH v4 20/42] hw/cxl/device: Add a memory device (8.2.8.5), Jonathan Cameron, 2022/01/24
- [PATCH v4 21/42] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Jonathan Cameron, 2022/01/24
- [PATCH v4 22/42] acpi/cxl: Add _OSC implementation (9.14.2), Jonathan Cameron, 2022/01/24
- [PATCH v4 23/42] tests/acpi: allow CEDT table addition, Jonathan Cameron, 2022/01/24
- [PATCH v4 24/42] acpi/cxl: Create the CEDT (9.14.1), Jonathan Cameron, 2022/01/24
- [PATCH v4 25/42] hw/cxl/device: Add some trivial commands, Jonathan Cameron, 2022/01/24
- [PATCH v4 26/42] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, Jonathan Cameron, 2022/01/24
- [PATCH v4 27/42] hw/cxl/device: Implement get/set Label Storage Area (LSA), Jonathan Cameron, 2022/01/24
- [PATCH v4 28/42] hw/cxl/component: Add utils for interleave parameter encoding/decoding,
Jonathan Cameron <=
- [PATCH v4 29/42] hw/cxl/host: Add support for CXL Fixed Memory Windows., Jonathan Cameron, 2022/01/24
- [PATCH v4 30/42] acpi/cxl: Introduce CFMWS structures in CEDT, Jonathan Cameron, 2022/01/24
- [PATCH v4 31/42] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Jonathan Cameron, 2022/01/24