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[PATCH v2 20/38] target/ppc: Move xxsel to decodetree
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From: |
matheus . ferst |
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Subject: |
[PATCH v2 20/38] target/ppc: Move xxsel to decodetree |
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Date: |
Tue, 25 Jan 2022 09:19:25 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 6 ++++
target/ppc/insn64.decode | 24 ++++++++--------
target/ppc/translate/vsx-impl.c.inc | 20 ++++++--------
target/ppc/translate/vsx-ops.c.inc | 43 -----------------------------
4 files changed, 26 insertions(+), 67 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2ebb441550..e56aec7636 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -148,12 +148,16 @@
%xx_xt 0:1 21:5
%xx_xb 1:1 11:5
%xx_xa 2:1 16:5
+%xx_xc 3:1 6:5
&XX2 xt xb uim:uint8_t
@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt
xb=%xx_xb
&XX3 xt xa xb
@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt
xa=%xx_xa xb=%xx_xb
+&XX4 xt xa xb xc
+@XX4 ...... ..... ..... ..... ..... .. .... &XX4 xt=%xx_xt
xa=%xx_xa xb=%xx_xb xc=%xx_xc
+
&Z22_bf_fra bf fra dm
@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
@@ -538,6 +542,8 @@ STXVPX 011111 ..... ..... ..... 0111001101 -
@X_TSXP
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
+XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4
+
## VSX Vector Load Special Value Instruction
LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 39e610913d..9e4f531fb9 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -44,15 +44,15 @@
...... ..... .... . ................ \
&8RR_D si=%8rr_si xt=%8rr_xt
-# Format XX4
-&XX4 xt xa xb xc
-%xx4_xt 0:1 21:5
-%xx4_xa 2:1 16:5
-%xx4_xb 1:1 11:5
-%xx4_xc 3:1 6:5
-@XX4 ........ ........ ........ ........ \
+# Format 8RR:XX4
+%8rr_xx_xt 0:1 21:5
+%8rr_xx_xa 2:1 16:5
+%8rr_xx_xb 1:1 11:5
+%8rr_xx_xc 3:1 6:5
+&8RR_XX4 xt xa xb xc
+@8RR_XX4 ........ ........ ........ ........ \
...... ..... ..... ..... ..... .. .... \
- &XX4 xt=%xx4_xt xa=%xx4_xa xb=%xx4_xb xc=%xx4_xc
+ &8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb
xc=%8rr_xx_xc
### Fixed-Point Load Instructions
@@ -187,10 +187,10 @@ XXSPLTI32DX 000001 01 0000 -- -- ................ \
100000 ..... 000 .. ................ @8RR_D_IX
XXBLENDVD 000001 01 0000 -- ------------------ \
- 100001 ..... ..... ..... ..... 11 .... @XX4
+ 100001 ..... ..... ..... ..... 11 .... @8RR_XX4
XXBLENDVW 000001 01 0000 -- ------------------ \
- 100001 ..... ..... ..... ..... 10 .... @XX4
+ 100001 ..... ..... ..... ..... 10 .... @8RR_XX4
XXBLENDVH 000001 01 0000 -- ------------------ \
- 100001 ..... ..... ..... ..... 01 .... @XX4
+ 100001 ..... ..... ..... ..... 01 .... @8RR_XX4
XXBLENDVB 000001 01 0000 -- ------------------ \
- 100001 ..... ..... ..... ..... 00 .... @XX4
+ 100001 ..... ..... ..... ..... 00 .... @8RR_XX4
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index b89be57272..83e3285e19 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1420,19 +1420,15 @@ static void glue(gen_, name)(DisasContext *ctx)
\
VSX_XXMRG(xxmrghw, 1)
VSX_XXMRG(xxmrglw, 0)
-static void gen_xxsel(DisasContext *ctx)
+static bool trans_XXSEL(DisasContext *ctx, arg_XX4 *a)
{
- int rt = xT(ctx->opcode);
- int ra = xA(ctx->opcode);
- int rb = xB(ctx->opcode);
- int rc = xC(ctx->opcode);
+ REQUIRE_INSNS_FLAGS2(ctx, VSX);
+ REQUIRE_VSX(ctx);
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(rt), vsr_full_offset(rc),
- vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);
+ tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(a->xt), vsr_full_offset(a->xc),
+ vsr_full_offset(a->xb), vsr_full_offset(a->xa), 16,
16);
+
+ return true;
}
static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
@@ -2125,7 +2121,7 @@ static void gen_xxblendv_vec(unsigned vece, TCGv_vec t,
TCGv_vec a, TCGv_vec b,
tcg_temp_free_vec(tmp);
}
-static bool do_xxblendv(DisasContext *ctx, arg_XX4 *a, unsigned vece)
+static bool do_xxblendv(DisasContext *ctx, arg_8RR_XX4 *a, unsigned vece)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_sari_vec, 0
diff --git a/target/ppc/translate/vsx-ops.c.inc
b/target/ppc/translate/vsx-ops.c.inc
index c974324c4c..b0dbb38c80 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -347,47 +347,4 @@ GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
-#define GEN_XXSEL_ROW(opc3) \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
-
-GEN_XXSEL_ROW(0x00)
-GEN_XXSEL_ROW(0x01)
-GEN_XXSEL_ROW(0x02)
-GEN_XXSEL_ROW(0x03)
-GEN_XXSEL_ROW(0x04)
-GEN_XXSEL_ROW(0x05)
-GEN_XXSEL_ROW(0x06)
-GEN_XXSEL_ROW(0x07)
-GEN_XXSEL_ROW(0x08)
-GEN_XXSEL_ROW(0x09)
-GEN_XXSEL_ROW(0x0A)
-GEN_XXSEL_ROW(0x0B)
-GEN_XXSEL_ROW(0x0C)
-GEN_XXSEL_ROW(0x0D)
-GEN_XXSEL_ROW(0x0E)
-GEN_XXSEL_ROW(0x0F)
-GEN_XXSEL_ROW(0x10)
-GEN_XXSEL_ROW(0x11)
-GEN_XXSEL_ROW(0x12)
-GEN_XXSEL_ROW(0x13)
-GEN_XXSEL_ROW(0x14)
-GEN_XXSEL_ROW(0x15)
-GEN_XXSEL_ROW(0x16)
-GEN_XXSEL_ROW(0x17)
-GEN_XXSEL_ROW(0x18)
-GEN_XXSEL_ROW(0x19)
-GEN_XXSEL_ROW(0x1A)
-GEN_XXSEL_ROW(0x1B)
-GEN_XXSEL_ROW(0x1C)
-GEN_XXSEL_ROW(0x1D)
-GEN_XXSEL_ROW(0x1E)
-GEN_XXSEL_ROW(0x1F)
-
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
--
2.25.1
- [PATCH v2 08/38] target/ppc: Implement vextsd2q, (continued)
- [PATCH v2 08/38] target/ppc: Implement vextsd2q, matheus . ferst, 2022/01/25
- [PATCH v2 07/38] target/ppc: Move vexts[bhw]2[wd] to decodetree, matheus . ferst, 2022/01/25
- [PATCH v2 09/38] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree, matheus . ferst, 2022/01/25
- [PATCH v2 11/38] target/ppc: Implement Vector Compare Equal Quadword, matheus . ferst, 2022/01/25
- [PATCH v2 12/38] target/ppc: Implement Vector Compare Greater Than Quadword, matheus . ferst, 2022/01/25
- [PATCH v2 13/38] target/ppc: Implement Vector Compare Quadword, matheus . ferst, 2022/01/25
- [PATCH v2 14/38] target/ppc: implement vstri[bh][lr], matheus . ferst, 2022/01/25
- [PATCH v2 15/38] target/ppc: implement vclrlb, matheus . ferst, 2022/01/25
- [PATCH v2 18/38] target/ppc: implement vgnb, matheus . ferst, 2022/01/25
- [PATCH v2 19/38] target/ppc: Move vsel and vperm/vpermr to decodetree, matheus . ferst, 2022/01/25
- [PATCH v2 20/38] target/ppc: Move xxsel to decodetree,
matheus . ferst <=
- [PATCH v2 17/38] target/ppc: implement vcntmb[bhwd], matheus . ferst, 2022/01/25
- [PATCH v2 16/38] target/ppc: implement vclrrb, matheus . ferst, 2022/01/25
- [PATCH v2 21/38] target/ppc: move xxperm/xxpermr to decodetree, matheus . ferst, 2022/01/25
- [PATCH v2 23/38] target/ppc: Implement xxpermx instruction, matheus . ferst, 2022/01/25
- [PATCH v2 22/38] target/ppc: Move xxpermdi to decodetree, matheus . ferst, 2022/01/25
- [PATCH v2 25/38] target/ppc: Implement xxeval, matheus . ferst, 2022/01/25
- [PATCH v2 24/38] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i, matheus . ferst, 2022/01/25
- [PATCH v2 26/38] target/ppc: Implement xxgenpcv[bhwd]m instruction, matheus . ferst, 2022/01/25
- [PATCH v2 27/38] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree, matheus . ferst, 2022/01/25
- [PATCH v2 28/38] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o], matheus . ferst, 2022/01/25