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Re: [PATCH v4 14/42] tests/acpi: allow DSDT.viot table changes.
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From: |
Alex Bennée |
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Subject: |
Re: [PATCH v4 14/42] tests/acpi: allow DSDT.viot table changes. |
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Date: |
Thu, 27 Jan 2022 14:06:42 +0000 |
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User-agent: |
mu4e 1.7.6; emacs 28.0.91 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:
> From: Jonathan Cameron <jonathan.cameron@huawei.com>
>
> The next patch unifies some of the PCI host bridge DSDT
> generation code and results in some minor changes to this file.
I'd just squash this in with the patch that makes the change...
otherwise you risk breaking bisectablility.
>
> Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
> b/tests/qtest/bios-tables-test-allowed-diff.h
> index dfb8523c8b..08a8095432 100644
> --- a/tests/qtest/bios-tables-test-allowed-diff.h
> +++ b/tests/qtest/bios-tables-test-allowed-diff.h
> @@ -1 +1,2 @@
> /* List of comma-separated changed AML files to ignore */
> +"tests/data/acpi/q35/DSDT.viot",
--
Alex Bennée
- Re: [PATCH v4 10/42] hw/cxl/device: Add log commands (8.2.9.4) + CEL, (continued)
- [PATCH v4 15/42] acpi/pci: Consolidate host bridge setup, Jonathan Cameron, 2022/01/24
- [PATCH v4 16/42] tests/acpi: Add update DSDT.viot, Jonathan Cameron, 2022/01/24
- [PATCH v4 17/42] cxl: Machine level control on whether CXL support is enabled, Jonathan Cameron, 2022/01/24
- [PATCH v4 18/42] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Jonathan Cameron, 2022/01/24
- [PATCH v4 19/42] hw/cxl/rp: Add a root port, Jonathan Cameron, 2022/01/24