Re: [PATCH v7 00/10] Xilinx Versal's PMC SLCR and OSPI support

[Peter Maydell]

On Fri, 21 Jan 2022 at 16:11, Francisco Iglesias
<francisco.iglesias@xilinx.com> wrote:
>
> Hi,
>
> This series attempts to add support for Xilinx Versal's PMC SLCR
> (system-level control registers) and OSPI flash memory controller to
> Xilinx Versal virt machine.
>
> The series start with adding a model of Versal's PMC SLCR and connecting
> the model to the Versal virt machine. The series then adds a couple of
> headers into the xlnx_csu_dma.h needed for building and reusing it later
> with the OSPI. The series thereafter introduces a DMA control interface
> and implements the interface in the xlnx_csu_dma for being able to reuse
> and control the DMA with the OSPI controller. Thereafter a model of
> Versal's OSPI controller is added and connected to the Versal virt
> machine. The series then ends with adding initial support for the Micron
> Xccelera mt35xu01g flash and flashes of this type are connected to the
> OSPI in the Versal virt machine.


Applied to target-arm.next, thanks. (I fixed the indent issue
Luc noticed in patch 6.)

-- PMM