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[PATCH v5 16/43] tests/acpi: Add update DSDT.viot
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From: |
Jonathan Cameron |
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Subject: |
[PATCH v5 16/43] tests/acpi: Add update DSDT.viot |
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Date: |
Wed, 2 Feb 2022 14:10:10 +0000 |
From: Jonathan Cameron <jonathan.cameron@huawei.com>
The consolidation of DSDT AML generation for PCI host bridges
lead to some minor ordering changes and the addition of _ADR
with a default of 0 for those case that didn't already have it.
Only DSDT.viot test is affected.
Changes all similar to:
Scope (\_SB)
{
Device (PC30)
{
- Name (_UID, 0x30) // _UID: Unique ID
Name (_BBN, 0x30) // _BBN: BIOS Bus Number
Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID:
Hardware ID
Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, 0x30) // _UID: Unique ID
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
---
tests/data/acpi/q35/DSDT.viot | Bin 9398 -> 9416 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --git a/tests/data/acpi/q35/DSDT.viot b/tests/data/acpi/q35/DSDT.viot
index
1c3b4da5cbe81ecab5e1ef50d383b561c5e0f55f..207ac5b9ae4c3a4bc0094c2242d1a1b08771b784
100644
GIT binary patch
delta 139
zcmdnydBT&+CD<k8gbD)#<CBeCu5zLdVlnZ-PVv!A?xF$C#s(bmPELMY6KfQhxC}No
z$Z0Y1qbM*kn0!E9nwKNq(Itq1BR<sAg-ZdbOrCM_F9mK?rG^HRr4><?3V@Yv4pmBI
F0sxp4B{u*7
delta 143
zcmX@%xy_TyCD<ion+gL1<MNGMu5zMYqA~HoPVv!Aj-mn1#s(bmp`I>WlVjy%CeC%7
z+^Kj^(SX5#0jQdxl0g7Ptr1kM!sPw((lEse3<_8k8$uNeOjb|?Dc;<vXwM7)8)+to
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index 08a8095432..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/DSDT.viot",
--
2.32.0
- [PATCH v5 06/43] hw/cxl/device: Implement basic mailbox (8.2.8.4), (continued)
- [PATCH v5 06/43] hw/cxl/device: Implement basic mailbox (8.2.8.4), Jonathan Cameron, 2022/02/02
- [PATCH v5 07/43] hw/cxl/device: Add memory device utilities, Jonathan Cameron, 2022/02/02
- [PATCH v5 08/43] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1), Jonathan Cameron, 2022/02/02
- [PATCH v5 09/43] hw/cxl/device: Timestamp implementation (8.2.9.3), Jonathan Cameron, 2022/02/02
- [PATCH v5 10/43] hw/cxl/device: Add log commands (8.2.9.4) + CEL, Jonathan Cameron, 2022/02/02
- [PATCH v5 11/43] hw/pxb: Use a type for realizing expanders, Jonathan Cameron, 2022/02/02
- [PATCH v5 12/43] hw/pci/cxl: Create a CXL bus type, Jonathan Cameron, 2022/02/02
- [PATCH v5 13/43] hw/pxb: Allow creation of a CXL PXB (host bridge), Jonathan Cameron, 2022/02/02
- [PATCH v5 14/43] tests/acpi: allow DSDT.viot table changes., Jonathan Cameron, 2022/02/02
- [PATCH v5 15/43] acpi/pci: Consolidate host bridge setup, Jonathan Cameron, 2022/02/02
- [PATCH v5 16/43] tests/acpi: Add update DSDT.viot,
Jonathan Cameron <=
- [PATCH v5 17/43] cxl: Machine level control on whether CXL support is enabled, Jonathan Cameron, 2022/02/02
- [PATCH v5 18/43] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Jonathan Cameron, 2022/02/02
- [PATCH v5 19/43] hw/cxl/rp: Add a root port, Jonathan Cameron, 2022/02/02
- [PATCH v5 20/43] hw/cxl/device: Add a memory device (8.2.8.5), Jonathan Cameron, 2022/02/02