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[PATCH v3 26/37] target/ppc: Implement xxgenpcv[bhwd]m instruction
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From: |
matheus . ferst |
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Subject: |
[PATCH v3 26/37] target/ppc: Implement xxgenpcv[bhwd]m instruction |
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Date: |
Thu, 10 Feb 2022 09:34:36 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/helper.h | 4 ++
target/ppc/insn32.decode | 10 ++++
target/ppc/int_helper.c | 84 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.c.inc | 29 ++++++++++
4 files changed, 127 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4cf8e0747d..78025d597e 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -501,6 +501,10 @@ DEF_HELPER_3(xvrspic, void, env, vsr, vsr)
DEF_HELPER_3(xvrspim, void, env, vsr, vsr)
DEF_HELPER_3(xvrspip, void, env, vsr, vsr)
DEF_HELPER_3(xvrspiz, void, env, vsr, vsr)
+DEF_HELPER_3(XXGENPCVBM, void, vsr, avr, tl)
+DEF_HELPER_3(XXGENPCVHM, void, vsr, avr, tl)
+DEF_HELPER_3(XXGENPCVWM, void, vsr, avr, tl)
+DEF_HELPER_3(XXGENPCVDM, void, vsr, avr, tl)
DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
DEF_HELPER_5(XXPERMX, void, vsr, vsr, vsr, vsr, tl)
DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 8f0627c529..ced6b273ca 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -119,6 +119,9 @@
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
%x_xt 0:1 21:5
+&X_imm5 xt imm:uint8_t vrb
+@X_imm5 ...... ..... imm:5 vrb:5 .......... . &X_imm5
xt=%x_xt
+
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8
xt=%x_xt
@@ -553,6 +556,13 @@ XXPERMDI 111100 ..... ..... ..... 0 .. 01010 ...
@XX3_dm
XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4
+## VSX Vector Generate PCV
+
+XXGENPCVBM 111100 ..... ..... ..... 1110010100 . @X_imm5
+XXGENPCVHM 111100 ..... ..... ..... 1110010101 . @X_imm5
+XXGENPCVWM 111100 ..... ..... ..... 1110110100 . @X_imm5
+XXGENPCVDM 111100 ..... ..... ..... 1110110101 . @X_imm5
+
## VSX Vector Load Special Value Instruction
LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 7e26d68f53..2fa37a91c9 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1210,6 +1210,90 @@ void helper_VPERMR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t
*b, ppc_avr_t *c)
*r = result;
}
+#define XXGENPCV(NAME, SZ) \
+void helper_##NAME(ppc_vsr_t *t, ppc_vsr_t *b, target_ulong imm) \
+{ \
+ ppc_vsr_t tmp = { .u64 = { 0, 0 } }; \
+ \
+ switch (imm) { \
+ case 0b00000: /* Big-Endian expansion */ \
+ /* Initialize tmp with the result of an all-zeros mask */ \
+ tmp.VsrD(0) = 0x1011121314151617; \
+ tmp.VsrD(1) = 0x18191A1B1C1D1E1F; \
+ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ if (b->VsrB(i) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0; k < SZ; k++) { \
+ tmp.VsrB(i + k) = j + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ break; \
+ case 0b00001: /* Big-Endian compression */ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ if (b->VsrB(i) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0; k < SZ; k++) { \
+ tmp.VsrB(j + k) = i + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ break; \
+ case 0b00010: /* Little-Endian expansion */ \
+ /* Initialize tmp with the result of an all-zeros mask */ \
+ tmp.VsrD(0) = 0x1F1E1D1C1B1A1918; \
+ tmp.VsrD(1) = 0x1716151413121110; \
+ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ /* Reverse indexing of "i" */ \
+ const int idx = ARRAY_SIZE(b->u8) - i - SZ; \
+ if (b->VsrB(idx) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0, rk = SZ - 1; k < SZ; k++, rk--) { \
+ tmp.VsrB(idx + rk) = j + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ break; \
+ case 0b00011: /* Little-Endian compression */ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ if (b->VsrB(ARRAY_SIZE(b->u8) - i - SZ) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0, rk = SZ - 1; k < SZ; k++, rk--) { \
+ /* Reverse indexing of "j" */ \
+ const int idx = ARRAY_SIZE(b->u8) - j - SZ; \
+ tmp.VsrB(idx + rk) = i + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ break; \
+ default: \
+ /* Translation code validates IMM before calling this helper */ \
+ g_assert_not_reached(); \
+ break; \
+ } \
+ \
+ *t = tmp; \
+}
+XXGENPCV(XXGENPCVBM, 1)
+XXGENPCV(XXGENPCVHM, 2)
+XXGENPCV(XXGENPCVWM, 4)
+XXGENPCV(XXGENPCVDM, 8)
+#undef XXGENPCV
+
#if defined(HOST_WORDS_BIGENDIAN)
#define VBPERMQ_INDEX(avr, i) ((avr)->u8[(i)])
#define VBPERMD_INDEX(i) (i)
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 662b08b465..22f48938cb 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1254,6 +1254,35 @@ static bool trans_XXPERMX(DisasContext *ctx,
arg_8RR_XX4_uim3 *a)
return true;
}
+static bool do_xxgenpcv(DisasContext *ctx, arg_X_imm5 *a,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv))
+{
+ TCGv_ptr xt, vrb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ if (a->imm & ~0x3) {
+ gen_invalid(ctx);
+ return true;
+ }
+
+ xt = gen_vsr_ptr(a->xt);
+ vrb = gen_avr_ptr(a->vrb);
+
+ gen_helper(xt, vrb, tcg_constant_tl(a->imm));
+
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(vrb);
+
+ return true;
+}
+
+TRANS(XXGENPCVBM, do_xxgenpcv, gen_helper_XXGENPCVBM)
+TRANS(XXGENPCVHM, do_xxgenpcv, gen_helper_XXGENPCVHM)
+TRANS(XXGENPCVWM, do_xxgenpcv, gen_helper_XXGENPCVWM)
+TRANS(XXGENPCVDM, do_xxgenpcv, gen_helper_XXGENPCVDM)
+
#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
--
2.31.1
- [PATCH v3 17/37] target/ppc: implement vcntmb[bhwd], (continued)
- [PATCH v3 17/37] target/ppc: implement vcntmb[bhwd], matheus . ferst, 2022/02/10
- [PATCH v3 16/37] target/ppc: implement vclrrb, matheus . ferst, 2022/02/10
- [PATCH v3 18/37] target/ppc: implement vgnb, matheus . ferst, 2022/02/10
- [PATCH v3 19/37] target/ppc: Move vsel and vperm/vpermr to decodetree, matheus . ferst, 2022/02/10
- [PATCH v3 20/37] target/ppc: Move xxsel to decodetree, matheus . ferst, 2022/02/10
- [PATCH v3 21/37] target/ppc: move xxperm/xxpermr to decodetree, matheus . ferst, 2022/02/10
- [PATCH v3 22/37] target/ppc: Move xxpermdi to decodetree, matheus . ferst, 2022/02/10
- [PATCH v3 23/37] target/ppc: Implement xxpermx instruction, matheus . ferst, 2022/02/10
- [PATCH v3 24/37] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i, matheus . ferst, 2022/02/10
- [PATCH v3 25/37] target/ppc: Implement xxeval, matheus . ferst, 2022/02/10
- [PATCH v3 26/37] target/ppc: Implement xxgenpcv[bhwd]m instruction,
matheus . ferst <=
- [PATCH v3 27/37] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree, matheus . ferst, 2022/02/10
- [PATCH v3 28/37] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o], matheus . ferst, 2022/02/10
- [PATCH v3 29/37] target/ppc: Implement xvtlsbb instruction, matheus . ferst, 2022/02/10
- [PATCH v3 30/37] target/ppc: Remove xscmpnedp instruction, matheus . ferst, 2022/02/10
- [PATCH v3 31/37] target/ppc: Refactor VSX_SCALAR_CMP_DP, matheus . ferst, 2022/02/10
- [PATCH v3 32/37] target/ppc: Implement xscmp{eq,ge,gt}qp, matheus . ferst, 2022/02/10
- [PATCH v3 33/37] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree, matheus . ferst, 2022/02/10
- [PATCH v3 34/37] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3, matheus . ferst, 2022/02/10
- [PATCH v3 35/37] target/ppc: Refactor VSX_MAX_MINC helper, matheus . ferst, 2022/02/10
- [PATCH v3 36/37] target/ppc: Implement xs{max,min}cqp, matheus . ferst, 2022/02/10