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[PULL 29/34] tcg/sparc: Improve code gen for shifted 32-bit constants
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From: |
Richard Henderson |
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Subject: |
[PULL 29/34] tcg/sparc: Improve code gen for shifted 32-bit constants |
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Date: |
Fri, 11 Feb 2022 12:30:54 +1100 |
We had code for checking for 13 and 21-bit shifted constants,
but we can do better and allow 32-bit shifted constants.
This is still 2 insns shorter than the full 64-bit sequence.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/sparc/tcg-target.c.inc | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index 7a8f20ee9a..ed2f4ecc40 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -462,17 +462,17 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type,
TCGReg ret,
return;
}
- /* A 21-bit constant, shifted. */
+ /* A 32-bit constant, shifted. */
lsb = ctz64(arg);
test = (tcg_target_long)arg >> lsb;
- if (check_fit_tl(test, 13)) {
- tcg_out_movi_imm13(s, ret, test);
- tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX);
- return;
- } else if (lsb > 10 && test == extract64(test, 0, 21)) {
+ if (lsb > 10 && test == extract64(test, 0, 21)) {
tcg_out_sethi(s, ret, test << 10);
tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX);
return;
+ } else if (test == (uint32_t)test || test == (int32_t)test) {
+ tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch);
+ tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX);
+ return;
}
/* A 64-bit constant decomposed into 2 32-bit pieces. */
--
2.25.1
- [PULL 16/34] tcg/loongarch64: Support raising sigbus for user-only, (continued)
- [PULL 16/34] tcg/loongarch64: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 18/34] tcg/arm: Remove use_armv5t_instructions, Richard Henderson, 2022/02/10
- [PULL 19/34] tcg/arm: Remove use_armv6_instructions, Richard Henderson, 2022/02/10
- [PULL 21/34] tcg/arm: Support unaligned access for softmmu, Richard Henderson, 2022/02/10
- [PULL 20/34] tcg/arm: Check alignment for ldrd and strd, Richard Henderson, 2022/02/10
- [PULL 22/34] tcg/arm: Reserve a register for guest_base, Richard Henderson, 2022/02/10
- [PULL 23/34] tcg/arm: Support raising sigbus for user-only, Richard Henderson, 2022/02/10
- [PULL 24/34] tcg/mips: Support unaligned access for user-only, Richard Henderson, 2022/02/10
- [PULL 25/34] tcg/mips: Support unaligned access for softmmu, Richard Henderson, 2022/02/10
- [PULL 28/34] tcg/sparc: Add scratch argument to tcg_out_movi_int, Richard Henderson, 2022/02/10
- [PULL 29/34] tcg/sparc: Improve code gen for shifted 32-bit constants,
Richard Henderson <=
- [PULL 27/34] tcg/sparc: Split out tcg_out_movi_imm32, Richard Henderson, 2022/02/10
- [PULL 30/34] tcg/sparc: Convert patch_reloc to return bool, Richard Henderson, 2022/02/10
- [PULL 32/34] tcg/sparc: Add tcg_out_jmpl_const for better tail calls, Richard Henderson, 2022/02/10
- [PULL 33/34] tcg/sparc: Support unaligned access for user-only, Richard Henderson, 2022/02/10
- [PULL 31/34] tcg/sparc: Use the constant pool for 64-bit constants, Richard Henderson, 2022/02/10
- [PULL 26/34] tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64, Richard Henderson, 2022/02/10
- [PULL 34/34] tests/tcg/multiarch: Add sigbus.c, Richard Henderson, 2022/02/10
- Re: [PULL 00/34] tcg patch queue, Peter Maydell, 2022/02/14