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[PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when availab
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From: |
Alistair Francis |
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Subject: |
[PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available |
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Date: |
Sat, 12 Feb 2022 10:00:18 +1000 |
From: Anup Patel <anup.patel@wdc.com>
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-17-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2643c8bc37..e3068d6126 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -212,8 +212,17 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
qemu_fdt_add_subnode(mc->fdt, intc_name);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
intc_phandles[cpu]);
- qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
- "riscv,cpu-intc");
+ if (riscv_feature(&s->soc[socket].harts[cpu].env,
+ RISCV_FEATURE_AIA)) {
+ static const char * const compat[2] = {
+ "riscv,cpu-intc-aia", "riscv,cpu-intc"
+ };
+ qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible",
+ (char **)&compat, ARRAY_SIZE(compat));
+ } else {
+ qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
+ "riscv,cpu-intc");
+ }
qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
--
2.34.1
- [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs, (continued)
- [PULL 13/40] target/riscv: Implement SGEIP bit in hip and hie CSRs, Alistair Francis, 2022/02/11
- [PULL 14/40] target/riscv: Implement hgeie and hgeip CSRs, Alistair Francis, 2022/02/11
- [PULL 15/40] target/riscv: Improve delivery of guest external interrupts, Alistair Francis, 2022/02/11
- [PULL 16/40] target/riscv: Allow setting CPU feature from machine/device emulation, Alistair Francis, 2022/02/11
- [PULL 17/40] target/riscv: Add AIA cpu feature, Alistair Francis, 2022/02/11
- [PULL 18/40] target/riscv: Add defines for AIA CSRs, Alistair Francis, 2022/02/11
- [PULL 19/40] target/riscv: Allow AIA device emulation to set ireg rmw callback, Alistair Francis, 2022/02/11
- [PULL 21/40] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Alistair Francis, 2022/02/11
- [PULL 20/40] target/riscv: Implement AIA local interrupt priorities, Alistair Francis, 2022/02/11
- [PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs, Alistair Francis, 2022/02/11
- [PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available,
Alistair Francis <=
- [PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs, Alistair Francis, 2022/02/11
- [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART, Alistair Francis, 2022/02/11
- [PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs, Alistair Francis, 2022/02/11
- [PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 2022/02/11
- [PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Alistair Francis, 2022/02/11
- [PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation, Alistair Francis, 2022/02/11
- [PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Alistair Francis, 2022/02/11
- [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation, Alistair Francis, 2022/02/11
- [PULL 33/40] docs/system: riscv: Document AIA options for virt machine, Alistair Francis, 2022/02/11
- [PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Alistair Francis, 2022/02/11