[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 33/40] docs/system: riscv: Document AIA options for virt machine
From: |
Alistair Francis |
Subject: |
[PULL 33/40] docs/system: riscv: Document AIA options for virt machine |
Date: |
Sat, 12 Feb 2022 10:00:24 +1000 |
From: Anup Patel <anup.patel@wdc.com>
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-23-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/virt.rst | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index fa016584bf..373645513a 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -63,6 +63,22 @@ The following machine-specific options are supported:
When this option is "on", ACLINT devices will be emulated instead of
SiFive CLINT. When not specified, this option is assumed to be "off".
+- aia=[none|aplic|aplic-imsic]
+
+ This option allows selecting interrupt controller defined by the AIA
+ (advanced interrupt architecture) specification. The "aia=aplic" selects
+ APLIC (advanced platform level interrupt controller) to handle wired
+ interrupts whereas the "aia=aplic-imsic" selects APLIC and IMSIC (incoming
+ message signaled interrupt controller) to handle both wired interrupts and
+ MSIs. When not specified, this option is assumed to be "none" which selects
+ SiFive PLIC to handle wired interrupts.
+
+- aia-guests=nnn
+
+ The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest
+ having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
+ the default number of per-HART VS-level AIA IMSIC pages is 0.
+
Running Linux kernel
--------------------
--
2.34.1
- [PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs, (continued)
- [PULL 22/40] target/riscv: Implement AIA hvictl and hviprioX CSRs, Alistair Francis, 2022/02/11
- [PULL 27/40] hw/riscv: virt: Use AIA INTC compatible string when available, Alistair Francis, 2022/02/11
- [PULL 26/40] target/riscv: Implement AIA IMSIC interface CSRs, Alistair Francis, 2022/02/11
- [PULL 28/40] target/riscv: Allow users to force enable AIA CSRs in HART, Alistair Francis, 2022/02/11
- [PULL 23/40] target/riscv: Implement AIA interrupt filtering CSRs, Alistair Francis, 2022/02/11
- [PULL 25/40] target/riscv: Implement AIA xiselect and xireg CSRs, Alistair Francis, 2022/02/11
- [PULL 24/40] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Alistair Francis, 2022/02/11
- [PULL 29/40] hw/intc: Add RISC-V AIA APLIC device emulation, Alistair Francis, 2022/02/11
- [PULL 30/40] hw/riscv: virt: Add optional AIA APLIC support to virt machine, Alistair Francis, 2022/02/11
- [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation, Alistair Francis, 2022/02/11
- [PULL 33/40] docs/system: riscv: Document AIA options for virt machine,
Alistair Francis <=
- [PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Alistair Francis, 2022/02/11
- [PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs, Alistair Francis, 2022/02/11
- [PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE, Alistair Francis, 2022/02/11
- [PULL 37/40] target/riscv: add support for svnapot extension, Alistair Francis, 2022/02/11
- [PULL 40/40] docs/system: riscv: Update description of CPU, Alistair Francis, 2022/02/11
- [PULL 39/40] target/riscv: add support for svpbmt extension, Alistair Francis, 2022/02/11
- [PULL 38/40] target/riscv: add support for svinval extension, Alistair Francis, 2022/02/11
- [PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64, Alistair Francis, 2022/02/11
- Re: [PULL 00/40] riscv-to-apply queue, Peter Maydell, 2022/02/15