Re: Holding RISCV CPUs in reset

[Peter Maydell]

On Tue, 15 Feb 2022 at 10:30, vysakh pillai <vysakhpillai@gmail.com> wrote:
>
> Hi,
>  In an SMP system like the sifive_u machine which has a RISCV  e_cpu as hart0 
> and a set of u_cpus as hart 1-N, is there a way to start just the hart0 and 
> hold the other CPUs in reset until explicitly released by hart0 SW?
>
>  I am working on a machine similar to the sifive_u machine that has a set of 
> control registers which are accessible by hart0 to release the other cores 
> from reset once the SoC level initialization is completed by the hart0 SW. 
> Currently, the CPUs spin if they have a non-zero mhartid, executing code from 
> resetvec.

I don't think the riscv code has support for this, but QEMU's
core machinery does because it's used by some arm boards,
so it shouldn't be too difficult to add the necessary riscv parts.

You can look at the handling of the 'start-powered-off' property:
the SoC model sets that on CPUs which do not start running
immediately. The target/riscv code may need some minor changes
to do something appropriate with it.
The power-controller device model on an arm board then starts CPUs
as required by calling arm_set_cpu_on() or similar. There will
need to be a riscv-specific version of that code too.

(We don't distinguish "starts powered off" from "starts held
in reset", because from QEMU's point of view both states are
the same: the CPU is not executing instructions.)

thanks
-- PMM