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Re: [PULL 00/40] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL 00/40] riscv-to-apply queue |
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Date: |
Tue, 15 Feb 2022 11:39:22 +0000 |
On Sat, 12 Feb 2022 at 00:07, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 0a301624c2f4ced3331ffd5bce85b4274fe132af:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20220208' into staging (2022-02-08
> 11:40:08 +0000)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220212
>
> for you to fetch changes up to 31d69b66ed89fa0f66d4e5a15e9664c92c3ed8f8:
>
> docs/system: riscv: Update description of CPU (2022-02-11 18:31:29 +1000)
>
> ----------------------------------------------------------------
> Fourth RISC-V PR for QEMU 7.0
>
> * Remove old Ibex PLIC header file
> * Allow writing 8 bytes with generic loader
> * Fixes for RV128
> * Refactor RISC-V CPU configs
> * Initial support for XVentanaCondOps custom extension
> * Fix for vill field in vtype
> * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
> * RISC-V AIA support for virt machine
> * Support for svnapot, svinval and svpbmt extensions
Hi; this has format string issues on 32-bit hosts:
https://gitlab.com/qemu-project/qemu/-/jobs/2092600735
../hw/riscv/virt.c: In function 'create_fdt_imsic':
../hw/riscv/virt.c:519:49: error: format '%lx' expects argument of
type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
long unsigned int'} [-Werror=format=]
../hw/riscv/virt.c:569:49: error: format '%lx' expects argument of
type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
long unsigned int'} [-Werror=format=]
Printing hwaddrs needs the HWADDR_PRIx macro. (%l and %ll are
usually the wrong thing in QEMU code as we don't often deal
with real 'long' or 'long long' types.)
-- PMM
- [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation, (continued)
- [PULL 31/40] hw/intc: Add RISC-V AIA IMSIC device emulation, Alistair Francis, 2022/02/11
- [PULL 33/40] docs/system: riscv: Document AIA options for virt machine, Alistair Francis, 2022/02/11
- [PULL 32/40] hw/riscv: virt: Add optional AIA IMSIC support to virt machine, Alistair Francis, 2022/02/11
- [PULL 34/40] hw/riscv: virt: Increase maximum number of allowed CPUs, Alistair Francis, 2022/02/11
- [PULL 36/40] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE, Alistair Francis, 2022/02/11
- [PULL 37/40] target/riscv: add support for svnapot extension, Alistair Francis, 2022/02/11
- [PULL 40/40] docs/system: riscv: Update description of CPU, Alistair Francis, 2022/02/11
- [PULL 39/40] target/riscv: add support for svpbmt extension, Alistair Francis, 2022/02/11
- [PULL 38/40] target/riscv: add support for svinval extension, Alistair Francis, 2022/02/11
- [PULL 35/40] target/riscv: Ignore reserved bits in PTE for RV64, Alistair Francis, 2022/02/11
- Re: [PULL 00/40] riscv-to-apply queue,
Peter Maydell <=