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Re: [PULL v2 00/35] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL v2 00/35] riscv-to-apply queue |
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Date: |
Wed, 16 Feb 2022 15:29:06 +0000 |
On Wed, 16 Feb 2022 at 07:13, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit ad38520bdeb2b1e0b487db317f29119e94c1c88d:
>
> Merge remote-tracking branch
> 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2022-02-15
> 19:30:33 +0000)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220216
>
> for you to fetch changes up to 7035b8420fa52e8c94cf4317c0f88c1b73ced28d:
>
> docs/system: riscv: Update description of CPU (2022-02-16 12:25:52 +1000)
>
> ----------------------------------------------------------------
> Fourth RISC-V PR for QEMU 7.0
>
> * Remove old Ibex PLIC header file
> * Allow writing 8 bytes with generic loader
> * Fixes for RV128
> * Refactor RISC-V CPU configs
> * Initial support for XVentanaCondOps custom extension
> * Fix for vill field in vtype
> * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
> * Support for svnapot, svinval and svpbmt extensions
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
- [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs, (continued)
- [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs, Alistair Francis, 2022/02/16
- [PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART, Alistair Francis, 2022/02/16
- [PULL v2 29/35] hw/intc: Add RISC-V AIA APLIC device emulation, Alistair Francis, 2022/02/16
- [PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available, Alistair Francis, 2022/02/16
- [PULL v2 30/35] target/riscv: Ignore reserved bits in PTE for RV64, Alistair Francis, 2022/02/16
- [PULL v2 31/35] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE, Alistair Francis, 2022/02/16
- [PULL v2 32/35] target/riscv: add support for svnapot extension, Alistair Francis, 2022/02/16
- [PULL v2 35/35] docs/system: riscv: Update description of CPU, Alistair Francis, 2022/02/16
- [PULL v2 33/35] target/riscv: add support for svinval extension, Alistair Francis, 2022/02/16
- [PULL v2 34/35] target/riscv: add support for svpbmt extension, Alistair Francis, 2022/02/16
- Re: [PULL v2 00/35] riscv-to-apply queue,
Peter Maydell <=