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[PATCH v6 37/43] hw/loongarch: Add some devices support for 3A5000.
From: |
Xiaojuan Yang |
Subject: |
[PATCH v6 37/43] hw/loongarch: Add some devices support for 3A5000. |
Date: |
Wed, 1 Jun 2022 18:25:03 +0800 |
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-64.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/loongarch/Kconfig | 7 ++++
hw/loongarch/loongson3.c | 77 ++++++++++++++++++++++++++++++++++++++
include/hw/pci-host/ls7a.h | 7 ++++
3 files changed, 91 insertions(+)
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index f779087416..8552ff4bee 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -2,6 +2,13 @@ config LOONGARCH_VIRT
bool
select PCI
select PCI_EXPRESS_GENERIC_BRIDGE
+ imply VGA_PCI
+ imply VIRTIO_VGA
+ imply PCI_DEVICES
+ select ISA_BUS
+ select SERIAL
+ select SERIAL_ISA
+ select VIRTIO_PCI
select LOONGARCH_IPI
select LOONGARCH_PCH_PIC
select LOONGARCH_PCH_MSI
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index 7a5c61e2df..7bc17113dc 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -9,6 +9,7 @@
#include "qemu/datadir.h"
#include "qapi/error.h"
#include "hw/boards.h"
+#include "hw/char/serial.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "sysemu/runstate.h"
@@ -16,14 +17,88 @@
#include "sysemu/rtc.h"
#include "hw/loongarch/virt.h"
#include "exec/address-spaces.h"
+#include "hw/irq.h"
+#include "net/net.h"
#include "hw/intc/loongarch_ipi.h"
#include "hw/intc/loongarch_extioi.h"
#include "hw/intc/loongarch_pch_pic.h"
#include "hw/intc/loongarch_pch_msi.h"
#include "hw/pci-host/ls7a.h"
+#include "hw/pci-host/gpex.h"
+#include "hw/misc/unimp.h"
#include "target/loongarch/cpu.h"
+static void loongarch_devices_init(DeviceState *pch_pic)
+{
+ DeviceState *gpex_dev;
+ SysBusDevice *d;
+ PCIBus *pci_bus;
+ MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg;
+ MemoryRegion *mmio_alias, *mmio_reg;
+ int i;
+
+ gpex_dev = qdev_new(TYPE_GPEX_HOST);
+ d = SYS_BUS_DEVICE(gpex_dev);
+ sysbus_realize_and_unref(d, &error_fatal);
+ pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus;
+
+ /* Map only part size_ecam bytes of ECAM space */
+ ecam_alias = g_new0(MemoryRegion, 1);
+ ecam_reg = sysbus_mmio_get_region(d, 0);
+ memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam",
+ ecam_reg, 0, LS_PCIECFG_SIZE);
+ memory_region_add_subregion(get_system_memory(), LS_PCIECFG_BASE,
+ ecam_alias);
+
+ /* Map PCI mem space */
+ mmio_alias = g_new0(MemoryRegion, 1);
+ mmio_reg = sysbus_mmio_get_region(d, 1);
+ memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio",
+ mmio_reg, LS7A_PCI_MEM_BASE, LS7A_PCI_MEM_SIZE);
+ memory_region_add_subregion(get_system_memory(), LS7A_PCI_MEM_BASE,
+ mmio_alias);
+
+ /* Map PCI IO port space. */
+ pio_alias = g_new0(MemoryRegion, 1);
+ pio_reg = sysbus_mmio_get_region(d, 2);
+ memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg,
+ LS7A_PCI_IO_OFFSET, LS7A_PCI_IO_SIZE);
+ memory_region_add_subregion(get_system_memory(), LS7A_PCI_IO_BASE,
+ pio_alias);
+
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
+ sysbus_connect_irq(d, i,
+ qdev_get_gpio_in(pch_pic, 16 + i));
+ gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
+ }
+
+ serial_mm_init(get_system_memory(), LS7A_UART_BASE, 0,
+ qdev_get_gpio_in(pch_pic,
+ LS7A_UART_IRQ - PCH_PIC_IRQ_OFFSET),
+ 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+
+ /* Network init */
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!nd->model) {
+ nd->model = g_strdup("virtio");
+ }
+
+ pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
+ }
+
+ /* VGA setup */
+ pci_vga_init(pci_bus);
+
+ /*
+ * There are some invalid guest memory access.
+ * Create some unimplemented devices to emulate this.
+ */
+ create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
+}
+
static void loongarch_irq_init(LoongArchMachineState *lams)
{
MachineState *ms = MACHINE(lams);
@@ -118,6 +193,8 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
qdev_connect_gpio_out(DEVICE(d), i,
qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
}
+
+ loongarch_devices_init(pch_pic);
}
static void loongarch_init(MachineState *machine)
diff --git a/include/hw/pci-host/ls7a.h b/include/hw/pci-host/ls7a.h
index 089d3e5438..5c653527f0 100644
--- a/include/hw/pci-host/ls7a.h
+++ b/include/hw/pci-host/ls7a.h
@@ -17,6 +17,11 @@
#define LS7A_PCI_MEM_BASE 0x40000000UL
#define LS7A_PCI_MEM_SIZE 0x40000000UL
+#define LS7A_PCI_IO_OFFSET 0x4000
+#define LS_PCIECFG_BASE 0x20000000
+#define LS_PCIECFG_SIZE 0x08000000
+#define LS7A_PCI_IO_BASE 0x18004000UL
+#define LS7A_PCI_IO_SIZE 0xC000
#define LS7A_PCH_REG_BASE 0x10000000UL
#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE)
@@ -30,4 +35,6 @@
#define PCH_PIC_IRQ_OFFSET 64
#define LS7A_DEVICE_IRQS 16
#define LS7A_PCI_IRQS 48
+#define LS7A_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
+#define LS7A_UART_BASE 0x1fe001e0
#endif
--
2.31.1
- [PATCH v6 31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI), (continued)
- [PATCH v6 31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI), Xiaojuan Yang, 2022/06/01
- [PATCH v6 35/43] hw/loongarch: Add irq hierarchy for the system, Xiaojuan Yang, 2022/06/01
- [PATCH v6 40/43] hw/loongarch: Add LoongArch power manager support, Xiaojuan Yang, 2022/06/01
- [PATCH v6 27/43] target/loongarch: Add TLB instruction support, Xiaojuan Yang, 2022/06/01
- [PATCH v6 43/43] target/loongarch: 'make check-tcg' support, Xiaojuan Yang, 2022/06/01
- [PATCH v6 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system, Xiaojuan Yang, 2022/06/01
- [PATCH v6 29/43] target/loongarch: Add timer related instructions support., Xiaojuan Yang, 2022/06/01
- [PATCH v6 17/43] target/loongarch: Add target build suport, Xiaojuan Yang, 2022/06/01
- [PATCH v6 19/43] target/loongarch: Add CSRs definition, Xiaojuan Yang, 2022/06/01
- [PATCH v6 37/43] hw/loongarch: Add some devices support for 3A5000.,
Xiaojuan Yang <=
- [PATCH v6 28/43] target/loongarch: Add other core instructions support, Xiaojuan Yang, 2022/06/01
- [PATCH v6 26/43] target/loongarch: Add LoongArch IOCSR instruction, Xiaojuan Yang, 2022/06/01
- [PATCH v6 16/43] target/loongarch: Add disassembler, Xiaojuan Yang, 2022/06/01
- [PATCH v6 30/43] hw/loongarch: Add support loongson3 virt machine type., Xiaojuan Yang, 2022/06/01
- [PATCH v6 22/43] target/loongarch: Add MMU support for LoongArch CPU., Xiaojuan Yang, 2022/06/01
- [PATCH v6 24/43] target/loongarch: Add constant timer support, Xiaojuan Yang, 2022/06/01
- [PATCH v6 14/43] target/loongarch: Add floating point load/store instruction translation, Xiaojuan Yang, 2022/06/01
- [PATCH v6 10/43] target/loongarch: Add floating point arithmetic instruction translation, Xiaojuan Yang, 2022/06/01
- [PATCH v6 12/43] target/loongarch: Add floating point conversion instruction translation, Xiaojuan Yang, 2022/06/01
- [PATCH v6 41/43] target/loongarch: Add gdb support., Xiaojuan Yang, 2022/06/01