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[PATCH 0/3] target/riscv: Fix issue 1060
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From: |
Richard Henderson |
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Subject: |
[PATCH 0/3] target/riscv: Fix issue 1060 |
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Date: |
Sat, 4 Jun 2022 23:10:01 +0000 |
This issue concerns the value of mtval for illegal
instruction exceptions, and came with a great test case.
The fix is just two lines, in the first patch, but
I noticed some cleanups on the way.
r~
Richard Henderson (3):
target/riscv: Set env->bins in gen_exception_illegal
target/riscv: Remove generate_exception_mtval
target/riscv: Minimize the calls to decode_save_opc
target/riscv/translate.c | 31 +++++------
.../riscv/insn_trans/trans_privileged.c.inc | 4 ++
target/riscv/insn_trans/trans_rvh.c.inc | 2 +
target/riscv/insn_trans/trans_rvi.c.inc | 2 +
tests/tcg/riscv64/Makefile.softmmu-target | 21 ++++++++
tests/tcg/riscv64/issue1060.S | 53 +++++++++++++++++++
tests/tcg/riscv64/semihost.ld | 21 ++++++++
7 files changed, 116 insertions(+), 18 deletions(-)
create mode 100644 tests/tcg/riscv64/Makefile.softmmu-target
create mode 100644 tests/tcg/riscv64/issue1060.S
create mode 100644 tests/tcg/riscv64/semihost.ld
--
2.34.1
- [PATCH 0/3] target/riscv: Fix issue 1060,
Richard Henderson <=
- [PATCH 1/3] target/riscv: Set env->bins in gen_exception_illegal, Richard Henderson, 2022/06/04
- [PATCH 3/3] target/riscv: Minimize the calls to decode_save_opc, Richard Henderson, 2022/06/04
- [PATCH 2/3] target/riscv: Remove generate_exception_mtval, Richard Henderson, 2022/06/04
- Re: [PATCH 0/3] target/riscv: Fix issue 1060, Richard Henderson, 2022/06/08
- Re: [PATCH 0/3] target/riscv: Fix issue 1060, Alistair Francis, 2022/06/15