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[PATCH v4] hw/cxl: Fix missing write mask for HDM decoder target list re
From: |
Jonathan Cameron |
Subject: |
[PATCH v4] hw/cxl: Fix missing write mask for HDM decoder target list registers |
Date: |
Wed, 8 Jun 2022 14:08:04 +0100 |
Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
---
v4: (Ben Widawsky review responses - thanks!)
- Expand list of matched types for 'skip' usages (with more restrictive
write mask) to include all CXL device types (type 3, type 1/2 and LD).
We only emulate type 3 so far but good for the function implementation
to be correct for the other types.
- Added Ben's RB.
hw/cxl/cxl-component-utils.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 7985c9bfca..3edd303a33 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -154,7 +154,8 @@ static void ras_init_common(uint32_t *reg_state, uint32_t
*write_msk)
reg_state[R_CXL_RAS_ERR_CAP_CTRL] = 0x00;
}
-static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
+static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk,
+ enum reg_type type)
{
int decoder_count = 1;
int i;
@@ -174,6 +175,14 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t
*write_msk)
write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
+ if (type == CXL2_DEVICE ||
+ type == CXL2_TYPE3_DEVICE ||
+ type == CXL2_LOGICAL_DEVICE) {
+ write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] =
0xf0000000;
+ } else {
+ write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] =
0xffffffff;
+ }
+ write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;
}
}
@@ -239,7 +248,7 @@ void cxl_component_register_init_common(uint32_t
*reg_state, uint32_t *write_msk
}
init_cap_reg(HDM, 5, 1);
- hdm_init_common(reg_state, write_msk);
+ hdm_init_common(reg_state, write_msk, type);
if (caps < 5) {
return;
--
2.32.0
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