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[PULL 28/55] target/arm: Move aa32_va_parameters to ptw.c
From: |
Peter Maydell |
Subject: |
[PULL 28/55] target/arm: Move aa32_va_parameters to ptw.c |
Date: |
Thu, 9 Jun 2022 10:05:10 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220604040607.269301-22-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.h | 3 ---
target/arm/helper.c | 64 ---------------------------------------------
target/arm/ptw.c | 64 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 64 insertions(+), 67 deletions(-)
diff --git a/target/arm/ptw.h b/target/arm/ptw.h
index a71161b01bd..9314fb4d23c 100644
--- a/target/arm/ptw.h
+++ b/target/arm/ptw.h
@@ -25,8 +25,5 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int
ap)
return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
}
-ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
- ARMMMUIdx mmu_idx);
-
#endif /* !CONFIG_USER_ONLY */
#endif /* TARGET_ARM_PTW_H */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2526f4c6c4a..f61f1da61e4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10771,70 +10771,6 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,
uint64_t va,
}
#ifndef CONFIG_USER_ONLY
-ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
- ARMMMUIdx mmu_idx)
-{
- uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
- uint32_t el = regime_el(env, mmu_idx);
- int select, tsz;
- bool epd, hpd;
-
- assert(mmu_idx != ARMMMUIdx_Stage2_S);
-
- if (mmu_idx == ARMMMUIdx_Stage2) {
- /* VTCR */
- bool sext = extract32(tcr, 4, 1);
- bool sign = extract32(tcr, 3, 1);
-
- /*
- * If the sign-extend bit is not the same as t0sz[3], the result
- * is unpredictable. Flag this as a guest error.
- */
- if (sign != sext) {
- qemu_log_mask(LOG_GUEST_ERROR,
- "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
- }
- tsz = sextract32(tcr, 0, 4) + 8;
- select = 0;
- hpd = false;
- epd = false;
- } else if (el == 2) {
- /* HTCR */
- tsz = extract32(tcr, 0, 3);
- select = 0;
- hpd = extract64(tcr, 24, 1);
- epd = false;
- } else {
- int t0sz = extract32(tcr, 0, 3);
- int t1sz = extract32(tcr, 16, 3);
-
- if (t1sz == 0) {
- select = va > (0xffffffffu >> t0sz);
- } else {
- /* Note that we will detect errors later. */
- select = va >= ~(0xffffffffu >> t1sz);
- }
- if (!select) {
- tsz = t0sz;
- epd = extract32(tcr, 7, 1);
- hpd = extract64(tcr, 41, 1);
- } else {
- tsz = t1sz;
- epd = extract32(tcr, 23, 1);
- hpd = extract64(tcr, 42, 1);
- }
- /* For aarch32, hpd0 is not enabled without t2e as well. */
- hpd &= extract32(tcr, 6, 1);
- }
-
- return (ARMVAParameters) {
- .tsz = tsz,
- .select = select,
- .epd = epd,
- .hpd = hpd,
- };
-}
-
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
MemTxAttrs *attrs)
{
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 525272e99af..427813ea563 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -615,6 +615,70 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx,
bool is_aa64,
return prot_rw | PAGE_EXEC;
}
+static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
+ ARMMMUIdx mmu_idx)
+{
+ uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
+ uint32_t el = regime_el(env, mmu_idx);
+ int select, tsz;
+ bool epd, hpd;
+
+ assert(mmu_idx != ARMMMUIdx_Stage2_S);
+
+ if (mmu_idx == ARMMMUIdx_Stage2) {
+ /* VTCR */
+ bool sext = extract32(tcr, 4, 1);
+ bool sign = extract32(tcr, 3, 1);
+
+ /*
+ * If the sign-extend bit is not the same as t0sz[3], the result
+ * is unpredictable. Flag this as a guest error.
+ */
+ if (sign != sext) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
+ }
+ tsz = sextract32(tcr, 0, 4) + 8;
+ select = 0;
+ hpd = false;
+ epd = false;
+ } else if (el == 2) {
+ /* HTCR */
+ tsz = extract32(tcr, 0, 3);
+ select = 0;
+ hpd = extract64(tcr, 24, 1);
+ epd = false;
+ } else {
+ int t0sz = extract32(tcr, 0, 3);
+ int t1sz = extract32(tcr, 16, 3);
+
+ if (t1sz == 0) {
+ select = va > (0xffffffffu >> t0sz);
+ } else {
+ /* Note that we will detect errors later. */
+ select = va >= ~(0xffffffffu >> t1sz);
+ }
+ if (!select) {
+ tsz = t0sz;
+ epd = extract32(tcr, 7, 1);
+ hpd = extract64(tcr, 41, 1);
+ } else {
+ tsz = t1sz;
+ epd = extract32(tcr, 23, 1);
+ hpd = extract64(tcr, 42, 1);
+ }
+ /* For aarch32, hpd0 is not enabled without t2e as well. */
+ hpd &= extract32(tcr, 6, 1);
+ }
+
+ return (ARMVAParameters) {
+ .tsz = tsz,
+ .select = select,
+ .epd = epd,
+ .hpd = hpd,
+ };
+}
+
/*
* check_s2_mmu_setup
* @cpu: ARMCPU
--
2.25.1
- [PULL 29/55] target/arm: Move ap_to_tw_prot etc to ptw.c, (continued)
- [PULL 29/55] target/arm: Move ap_to_tw_prot etc to ptw.c, Peter Maydell, 2022/06/09
- [PULL 24/55] target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_helper.c, Peter Maydell, 2022/06/09
- [PULL 34/55] target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx to ptw.c, Peter Maydell, 2022/06/09
- [PULL 38/55] target/arm: Remove route_to_el2 check from sve_exception_el, Peter Maydell, 2022/06/09
- [PULL 41/55] target/arm: Use el_is_in_host for sve_zcr_len_for_el, Peter Maydell, 2022/06/09
- [PULL 04/55] xlnx_dp: fix the wrong register size, Peter Maydell, 2022/06/09
- [PULL 15/55] target/arm: Move get_phys_addr_pmsav8 to ptw.c, Peter Maydell, 2022/06/09
- [PULL 19/55] target/arm: Move m_is_{ppb,system}_region to ptw.c, Peter Maydell, 2022/06/09
- [PULL 21/55] target/arm: Move combine_cacheattrs and subroutines to ptw.c, Peter Maydell, 2022/06/09
- [PULL 27/55] target/arm: Move check_s2_mmu_setup to ptw.c, Peter Maydell, 2022/06/09
- [PULL 28/55] target/arm: Move aa32_va_parameters to ptw.c,
Peter Maydell <=
- [PULL 36/55] target/arm: Rename TBFLAG_A64 ZCR_LEN to VL, Peter Maydell, 2022/06/09
- [PULL 01/55] target/arm: Declare support for FEAT_RASv1p1, Peter Maydell, 2022/06/09
- [PULL 10/55] target/arm: Move get_phys_addr_v5 to ptw.c, Peter Maydell, 2022/06/09
- [PULL 17/55] target/arm: Move pmsav7_use_background_region to ptw.c, Peter Maydell, 2022/06/09
- [PULL 30/55] target/arm: Move regime_is_user to ptw.c, Peter Maydell, 2022/06/09
- [PULL 35/55] target/arm: Pass CPUARMState to arm_ld[lq]_ptw, Peter Maydell, 2022/06/09
- [PULL 33/55] target/arm: Move arm_cpu_get_phys_page_attrs_debug to ptw.c, Peter Maydell, 2022/06/09
- [PULL 26/55] target/arm: Move get_S1prot, get_S2prot to ptw.c, Peter Maydell, 2022/06/09
- [PULL 43/55] target/arm: Hoist arm_is_el2_enabled check in sve_exception_el, Peter Maydell, 2022/06/09
- [PULL 42/55] target/arm: Use el_is_in_host for sve_exception_el, Peter Maydell, 2022/06/09