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[PULL 39/55] target/arm: Remove fp checks from sve_exception_el
From: |
Peter Maydell |
Subject: |
[PULL 39/55] target/arm: Remove fp checks from sve_exception_el |
Date: |
Thu, 9 Jun 2022 10:05:21 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Instead of checking these bits in fp_exception_el and
also in sve_exception_el, document that we must compare
the results. The only place where we have not already
checked that FP EL is zero is in rebuild_hflags_a64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220607203306.657998-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 58 +++++++++++++++------------------------------
1 file changed, 19 insertions(+), 39 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 1bd77af7e50..4f4044c688d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6129,11 +6129,15 @@ static const ARMCPRegInfo minimal_ras_reginfo[] = {
.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.vsesr_el2) },
};
-/* Return the exception level to which exceptions should be taken
- * via SVEAccessTrap. If an exception should be routed through
- * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
- * take care of raising that exception.
- * C.f. the ARM pseudocode function CheckSVEEnabled.
+/*
+ * Return the exception level to which exceptions should be taken
+ * via SVEAccessTrap. This excludes the check for whether the exception
+ * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
+ * be found by testing 0 < fp_exception_el < sve_exception_el.
+ *
+ * C.f. the ARM pseudocode function CheckSVEEnabled. Note that the
+ * pseudocode does *not* separate out the FP trap checks, but has them
+ * all in one function.
*/
int sve_exception_el(CPUARMState *env, int el)
{
@@ -6151,18 +6155,6 @@ int sve_exception_el(CPUARMState *env, int el)
case 2:
return 1;
}
-
- /* Check CPACR.FPEN. */
- switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN)) {
- case 1:
- if (el != 0) {
- break;
- }
- /* fall through */
- case 0:
- case 2:
- return 0;
- }
}
/*
@@ -6180,24 +6172,10 @@ int sve_exception_el(CPUARMState *env, int el)
case 2:
return 2;
}
-
- switch (FIELD_EX32(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) {
- case 1:
- if (el == 2 || !(hcr_el2 & HCR_TGE)) {
- break;
- }
- /* fall through */
- case 0:
- case 2:
- return 0;
- }
} else if (arm_is_el2_enabled(env)) {
if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) {
return 2;
}
- if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) {
- return 0;
- }
}
}
@@ -11168,19 +11146,21 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState
*env, int el, int fp_el,
if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
int sve_el = sve_exception_el(env, el);
- uint32_t zcr_len;
/*
- * If SVE is disabled, but FP is enabled,
- * then the effective len is 0.
+ * If either FP or SVE are disabled, translator does not need len.
+ * If SVE EL > FP EL, FP exception has precedence, and translator
+ * does not need SVE EL. Save potential re-translations by forcing
+ * the unneeded data to zero.
*/
- if (sve_el != 0 && fp_el == 0) {
- zcr_len = 0;
- } else {
- zcr_len = sve_zcr_len_for_el(env, el);
+ if (fp_el != 0) {
+ if (sve_el > fp_el) {
+ sve_el = 0;
+ }
+ } else if (sve_el == 0) {
+ DP_TBFLAG_A64(flags, VL, sve_zcr_len_for_el(env, el));
}
DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
- DP_TBFLAG_A64(flags, VL, zcr_len);
}
sctlr = regime_sctlr(env, stage1);
--
2.25.1
- [PULL 26/55] target/arm: Move get_S1prot, get_S2prot to ptw.c, (continued)
- [PULL 26/55] target/arm: Move get_S1prot, get_S2prot to ptw.c, Peter Maydell, 2022/06/09
- [PULL 43/55] target/arm: Hoist arm_is_el2_enabled check in sve_exception_el, Peter Maydell, 2022/06/09
- [PULL 42/55] target/arm: Use el_is_in_host for sve_exception_el, Peter Maydell, 2022/06/09
- [PULL 44/55] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset, Peter Maydell, 2022/06/09
- [PULL 46/55] target/arm: Use uint32_t instead of bitmap for sve vq's, Peter Maydell, 2022/06/09
- [PULL 49/55] target/arm: Export sve contiguous ldst support functions, Peter Maydell, 2022/06/09
- [PULL 51/55] target/arm: Use expand_pred_b in mve_helper.c, Peter Maydell, 2022/06/09
- [PULL 53/55] target/arm: Export bfdotadd from vec_helper.c, Peter Maydell, 2022/06/09
- [PULL 55/55] target/arm: Add ID_AA64SMFR0_EL1, Peter Maydell, 2022/06/09
- [PULL 54/55] target/arm: Add isar_feature_aa64_sme, Peter Maydell, 2022/06/09
- [PULL 39/55] target/arm: Remove fp checks from sve_exception_el,
Peter Maydell <=
- [PULL 45/55] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller, Peter Maydell, 2022/06/09
- [PULL 47/55] target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el, Peter Maydell, 2022/06/09
- [PULL 48/55] target/arm: Split out load/store primitives to sve_ldst_internal.h, Peter Maydell, 2022/06/09
- [PULL 52/55] target/arm: Move expand_pred_h to vec_internal.h, Peter Maydell, 2022/06/09
- [PULL 40/55] target/arm: Add el_is_in_host, Peter Maydell, 2022/06/09
- [PULL 37/55] linux-user/aarch64: Introduce sve_vq, Peter Maydell, 2022/06/09
- [PULL 50/55] target/arm: Move expand_pred_b to vec_internal.h, Peter Maydell, 2022/06/09
- Re: [PULL 00/55] target-arm queue, Richard Henderson, 2022/06/09