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[PULL 06/25] target/riscv: Wake on VS-level external interrupts
From: |
Alistair Francis |
Subject: |
[PULL 06/25] target/riscv: Wake on VS-level external interrupts |
Date: |
Fri, 10 Jun 2022 14:26:36 +1000 |
From: Andrew Bresticker <abrestic@rivosinc.com>
Whether or not VSEIP is pending isn't reflected in env->mip and must
instead be determined from hstatus.vgein and hgeip. As a result a
CPU in WFI won't wake on a VSEIP, which violates the WFI behavior as
specified in the privileged ISA. Just use riscv_cpu_all_pending()
instead, which already accounts for VSEIP.
Signed-off-by: Andrew Bresticker <abrestic@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220531210544.181322-1-abrestic@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 2 +-
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 890d33cebb..194a58d760 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -489,6 +489,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray
*buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
uint8_t riscv_cpu_default_priority(int irq);
+uint64_t riscv_cpu_all_pending(CPURISCVState *env);
int riscv_cpu_mirq_pending(CPURISCVState *env);
int riscv_cpu_sirq_pending(CPURISCVState *env);
int riscv_cpu_vsirq_pending(CPURISCVState *env);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bcbba3fbd5..0497af45cc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -391,7 +391,7 @@ static bool riscv_cpu_has_work(CPUState *cs)
* Definition of the WFI instruction requires it to ignore the privilege
* mode and delegation registers, but respect individual enables
*/
- return (env->mip & env->mie) != 0;
+ return riscv_cpu_all_pending(env) != 0;
#else
return true;
#endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d99fac9d2d..16c6045459 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -340,7 +340,7 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
return best_irq;
}
-static uint64_t riscv_cpu_all_pending(CPURISCVState *env)
+uint64_t riscv_cpu_all_pending(CPURISCVState *env)
{
uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
--
2.36.1
- [PULL 00/25] riscv-to-apply queue, Alistair Francis, 2022/06/10
- [PULL 01/25] MAINTAINERS: Cover hw/core/uboot_image.h within Generic Loader section, Alistair Francis, 2022/06/10
- [PULL 02/25] target/riscv: add support for zmmul extension v0.1, Alistair Francis, 2022/06/10
- [PULL 03/25] hw/riscv: virt: Generate fw_cfg DT node correctly, Alistair Francis, 2022/06/10
- [PULL 04/25] hw/intc: sifive_plic: Avoid overflowing the addr_config buffer, Alistair Francis, 2022/06/10
- [PULL 05/25] hw/core/loader: return image sizes as ssize_t, Alistair Francis, 2022/06/10
- [PULL 06/25] target/riscv: Wake on VS-level external interrupts,
Alistair Francis <=
- [PULL 07/25] target/riscv/debug.c: keep experimental rv128 support working, Alistair Francis, 2022/06/10
- [PULL 08/25] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, Alistair Francis, 2022/06/10
- [PULL 11/25] target/riscv: rvv: Early exit when vstart >= vl, Alistair Francis, 2022/06/10
- [PULL 09/25] target/riscv: rvv: Prune redundant access_type parameter passed, Alistair Francis, 2022/06/10
- [PULL 13/25] target/riscv: rvv: Add tail agnostic for vector load / store instructions, Alistair Francis, 2022/06/10
- [PULL 12/25] target/riscv: rvv: Add tail agnostic for vv instructions, Alistair Francis, 2022/06/10
- [PULL 17/25] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, Alistair Francis, 2022/06/10
- [PULL 10/25] target/riscv: rvv: Rename ambiguous esz, Alistair Francis, 2022/06/10
- [PULL 16/25] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, Alistair Francis, 2022/06/10
- [PULL 14/25] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, Alistair Francis, 2022/06/10