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[PULL 02/28] target/arm: Add coproc parameter to syn_fp_access_trap
From: |
Peter Maydell |
Subject: |
[PULL 02/28] target/arm: Add coproc parameter to syn_fp_access_trap |
Date: |
Fri, 10 Jun 2022 17:07:12 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
With ARMv8, this field is always RES0.
With ARMv7, targeting EL2 and TA=0, it is always 0xA.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220609202901.1177572-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/syndrome.h | 7 ++++---
target/arm/translate-a64.c | 3 ++-
target/arm/translate-vfp.c | 14 ++++++++++++--
3 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index 0cb26dde7d8..c105f9e6ba5 100644
--- a/target/arm/syndrome.h
+++ b/target/arm/syndrome.h
@@ -185,12 +185,13 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int
cond, int opc1, int crm,
| (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
}
-static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
+static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit,
+ int coproc)
{
- /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */
+ /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 */
return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
| (is_16bit ? 0 : ARM_EL_IL)
- | (cv << 24) | (cond << 20) | 0xa;
+ | (cv << 24) | (cond << 20) | coproc;
}
static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d438fb89e73..e7525890902 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1162,7 +1162,8 @@ static bool fp_access_check(DisasContext *s)
s->fp_access_checked = true;
gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
+ syn_fp_access_trap(1, 0xe, false, 0),
+ s->fp_excp_el);
return false;
}
s->fp_access_checked = true;
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index 40a513b8221..0f797c56fd8 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -219,8 +219,18 @@ static void gen_update_fp_context(DisasContext *s)
static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled)
{
if (s->fp_excp_el) {
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
- syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
+ /*
+ * The full syndrome is only used for HSR when HCPTR traps:
+ * For v8, when TA==0, coproc is RES0.
+ * For v7, any use of a Floating-point instruction or access
+ * to a Floating-point Extension register that is trapped to
+ * Hyp mode because of a trap configured in the HCPTR sets
+ * this field to 0xA.
+ */
+ int coproc = arm_dc_feature(s, ARM_FEATURE_V8) ? 0 : 0xa;
+ uint32_t syn = syn_fp_access_trap(1, 0xe, false, coproc);
+
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn, s->fp_excp_el);
return false;
}
--
2.25.1
- [PULL 00/28] target-arm queue, Peter Maydell, 2022/06/10
- [PULL 02/28] target/arm: Add coproc parameter to syn_fp_access_trap,
Peter Maydell <=
- [PULL 01/28] target/arm: Mark exception helpers as noreturn, Peter Maydell, 2022/06/10
- [PULL 04/28] target/arm: Move arm_singlestep_active out of line, Peter Maydell, 2022/06/10
- [PULL 05/28] target/arm: Move arm_generate_debug_exceptions out of line, Peter Maydell, 2022/06/10
- [PULL 08/28] target/arm: Move arm_debug_exception_fsr to debug_helper.c, Peter Maydell, 2022/06/10
- [PULL 09/28] target/arm: Rename helper_exception_with_syndrome, Peter Maydell, 2022/06/10
- [PULL 12/28] target/arm: Introduce gen_exception_insn, Peter Maydell, 2022/06/10
- [PULL 11/28] target/arm: Rename gen_exception_insn to gen_exception_insn_el, Peter Maydell, 2022/06/10
- [PULL 03/28] target/arm: Move exception_target_el out of line, Peter Maydell, 2022/06/10
- [PULL 06/28] target/arm: Use is_a64 in arm_generate_debug_exceptions, Peter Maydell, 2022/06/10
- [PULL 10/28] target/arm: Introduce gen_exception_insn_el_v, Peter Maydell, 2022/06/10