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[PULL 12/49] target/mips: Fix handling of unaligned memory access for na
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 12/49] target/mips: Fix handling of unaligned memory access for nanoMIPS ISA |
Date: |
Sat, 11 Jun 2022 12:32:35 +0200 |
From: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
nanoMIPS ISA does not support unaligned memory access. Adjust
DisasContext's default_tcg_memop_mask to reflect this.
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220504110403.613168-6-stefan.pejic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6de5b66650..5f460fb687 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -16023,8 +16023,9 @@ static void mips_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
#else
ctx->mem_idx = hflags_mmu_index(ctx->hflags);
#endif
- ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
- INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
+ ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&
+ (ctx->insn_flags & (ISA_MIPS_R6 |
+ INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN;
/*
* Execute a branch and its delay slot as a single instruction.
--
2.36.1
- [PULL 02/49] target/mips: Fix SAT_S trans helper, (continued)
- [PULL 02/49] target/mips: Fix SAT_S trans helper, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 03/49] target/mips: Fix df_extract_val() and df_extract_df() dfe lookup, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 04/49] target/mips: Fix msa checking condition in trans_msa_elm_fn(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 05/49] target/mips: Do not treat msa INSERT as NOP when wd is zero, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 06/49] target/mips: Fix store adress of high 64bit in helper_msa_st_b(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 07/49] target/mips: Fix FTRUNC_S and FTRUNC_U trans helper, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 08/49] target/mips: Fix emulation of nanoMIPS MTHLIP instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 09/49] target/mips: Fix emulation of nanoMIPS EXTRV_S.H instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 10/49] target/mips: Fix emulation of nanoMIPS BPOSGE32C instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 11/49] target/mips: Fix emulation of nanoMIPS BNEC[32] instruction, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 12/49] target/mips: Fix handling of unaligned memory access for nanoMIPS ISA,
Philippe Mathieu-Daudé <=
- [PULL 13/49] target/mips: Add missing default cases for some nanoMIPS pools, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 14/49] target/mips: Undeprecate nanoMIPS ISA support in QEMU, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 15/49] hw/block/fdc-sysbus: Always mark sysbus floppy controllers as not having DMA, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 16/49] hw/acpi/piix4: move xen_enabled() logic from piix4_pm_init() to piix4_pm_realize(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 17/49] hw/acpi/piix4: change smm_enabled from int to bool, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 18/49] hw/acpi/piix4: convert smm_enabled bool to qdev property, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 19/49] hw/acpi/piix4: move PIIX4PMState into separate piix4.h header, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 20/49] hw/acpi/piix4: alter piix4_pm_init() to return PIIX4PMState, Philippe Mathieu-Daudé, 2022/06/11
- [PULL 21/49] hw/acpi/piix4: rename piix4_pm_init() to piix4_pm_initfn(), Philippe Mathieu-Daudé, 2022/06/11
- [PULL 22/49] hw/acpi/piix4: use qdev gpio to wire up sci_irq, Philippe Mathieu-Daudé, 2022/06/11