[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v10 03/12] target/riscv: pmu: Rename the counters extension to pm
From: |
Atish Patra |
Subject: |
[PATCH v10 03/12] target/riscv: pmu: Rename the counters extension to pmu |
Date: |
Mon, 20 Jun 2022 16:15:53 -0700 |
From: Atish Patra <atish.patra@wdc.com>
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.c | 4 ++--
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 05e652135171..1b57b3c43980 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -851,7 +851,7 @@ static void riscv_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
- cpu->cfg.ext_counters = true;
+ cpu->cfg.ext_pmu = true;
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.mmu = true;
@@ -879,7 +879,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7d6397acdfb1..252c30a55d78 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -397,7 +397,7 @@ struct RISCVCPUConfig {
bool ext_zksed;
bool ext_zksh;
bool ext_zkt;
- bool ext_counters;
+ bool ext_pmu;
bool ext_ifencei;
bool ext_icsr;
bool ext_svinval;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 58d07c511f98..0ca05c77883c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -74,8 +74,8 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index;
- if (!cpu->cfg.ext_counters) {
- /* The Counters extensions is not enabled */
+ if (!cpu->cfg.ext_pmu) {
+ /* The PMU extension is not enabled */
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.25.1
- [PATCH v10 00/12] Improve PMU support, Atish Patra, 2022/06/20
- [PATCH v10 01/12] target/riscv: Fix PMU CSR predicate function, Atish Patra, 2022/06/20
- [PATCH v10 04/12] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2022/06/20
- [PATCH v10 02/12] target/riscv: Implement PMU CSR predicate function for S-mode, Atish Patra, 2022/06/20
- [PATCH v10 03/12] target/riscv: pmu: Rename the counters extension to pmu,
Atish Patra <=
- [PATCH v10 06/12] target/riscv: Add support for hpmcounters/hpmevents, Atish Patra, 2022/06/20
- [PATCH v10 10/12] target/riscv: Add few cache related PMU events, Atish Patra, 2022/06/20
- [PATCH v10 11/12] hw/riscv: virt: Add PMU DT node to the device tree, Atish Patra, 2022/06/20
- [PATCH v10 05/12] target/riscv: Implement mcountinhibit CSR, Atish Patra, 2022/06/20
- [PATCH v10 07/12] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2022/06/20
- [PATCH v10 08/12] target/riscv: Add sscofpmf extension support, Atish Patra, 2022/06/20
- [PATCH v10 09/12] target/riscv: Simplify counter predicate function, Atish Patra, 2022/06/20
- [PATCH v10 12/12] target/riscv: Update the privilege field for sscofpmf CSRs, Atish Patra, 2022/06/20