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[PULL 24/60] semihosting: Split out common-semi-target.h
From: |
Richard Henderson |
Subject: |
[PULL 24/60] semihosting: Split out common-semi-target.h |
Date: |
Tue, 28 Jun 2022 10:23:27 +0530 |
Move the ARM and RISCV specific helpers into
their own header file.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Luc Michel <lmichel@kalray.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/common-semi-target.h | 62 ++++++++++++++++++++
target/riscv/common-semi-target.h | 50 ++++++++++++++++
semihosting/arm-compat-semi.c | 94 +------------------------------
3 files changed, 113 insertions(+), 93 deletions(-)
create mode 100644 target/arm/common-semi-target.h
create mode 100644 target/riscv/common-semi-target.h
diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-target.h
new file mode 100644
index 0000000000..629d75ca5a
--- /dev/null
+++ b/target/arm/common-semi-target.h
@@ -0,0 +1,62 @@
+/*
+ * Target-specific parts of semihosting/arm-compat-semi.c.
+ *
+ * Copyright (c) 2005, 2007 CodeSourcery.
+ * Copyright (c) 2019, 2022 Linaro
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef TARGET_ARM_COMMON_SEMI_TARGET_H
+#define TARGET_ARM_COMMON_SEMI_TARGET_H
+
+#ifndef CONFIG_USER_ONLY
+#include "hw/arm/boot.h"
+#endif
+
+static inline target_ulong common_semi_arg(CPUState *cs, int argno)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ if (is_a64(env)) {
+ return env->xregs[argno];
+ } else {
+ return env->regs[argno];
+ }
+}
+
+static inline void common_semi_set_ret(CPUState *cs, target_ulong ret)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ if (is_a64(env)) {
+ env->xregs[0] = ret;
+ } else {
+ env->regs[0] = ret;
+ }
+}
+
+static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr)
+{
+ return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr));
+}
+
+static inline bool is_64bit_semihosting(CPUArchState *env)
+{
+ return is_a64(env);
+}
+
+static inline target_ulong common_semi_stack_bottom(CPUState *cs)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ return is_a64(env) ? env->xregs[31] : env->regs[13];
+}
+
+static inline bool common_semi_has_synccache(CPUArchState *env)
+{
+ /* Ok for A64, invalid for A32/T32 */
+ return is_a64(env);
+}
+
+#endif
diff --git a/target/riscv/common-semi-target.h
b/target/riscv/common-semi-target.h
new file mode 100644
index 0000000000..7c8a59e0cc
--- /dev/null
+++ b/target/riscv/common-semi-target.h
@@ -0,0 +1,50 @@
+/*
+ * Target-specific parts of semihosting/arm-compat-semi.c.
+ *
+ * Copyright (c) 2005, 2007 CodeSourcery.
+ * Copyright (c) 2019, 2022 Linaro
+ * Copyright © 2020 by Keith Packard <keithp@keithp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef TARGET_RISCV_COMMON_SEMI_TARGET_H
+#define TARGET_RISCV_COMMON_SEMI_TARGET_H
+
+static inline target_ulong common_semi_arg(CPUState *cs, int argno)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ return env->gpr[xA0 + argno];
+}
+
+static inline void common_semi_set_ret(CPUState *cs, target_ulong ret)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ env->gpr[xA0] = ret;
+}
+
+static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr)
+{
+ return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8);
+}
+
+static inline bool is_64bit_semihosting(CPUArchState *env)
+{
+ return riscv_cpu_mxl(env) != MXL_RV32;
+}
+
+static inline target_ulong common_semi_stack_bottom(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ return env->gpr[xSP];
+}
+
+static inline bool common_semi_has_synccache(CPUArchState *env)
+{
+ return true;
+}
+
+#endif
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index 50f40a2a1a..5e442e549d 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -46,9 +46,6 @@
#else
#include "qemu/cutils.h"
#include "hw/loader.h"
-#ifdef TARGET_ARM
-#include "hw/arm/boot.h"
-#endif
#include "hw/boards.h"
#endif
@@ -182,96 +179,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs)
#endif
-#ifdef TARGET_ARM
-static inline target_ulong
-common_semi_arg(CPUState *cs, int argno)
-{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
- if (is_a64(env)) {
- return env->xregs[argno];
- } else {
- return env->regs[argno];
- }
-}
-
-static inline void
-common_semi_set_ret(CPUState *cs, target_ulong ret)
-{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
- if (is_a64(env)) {
- env->xregs[0] = ret;
- } else {
- env->regs[0] = ret;
- }
-}
-
-static inline bool
-common_semi_sys_exit_extended(CPUState *cs, int nr)
-{
- return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr));
-}
-
-static inline bool is_64bit_semihosting(CPUArchState *env)
-{
- return is_a64(env);
-}
-
-static inline target_ulong common_semi_stack_bottom(CPUState *cs)
-{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
- return is_a64(env) ? env->xregs[31] : env->regs[13];
-}
-
-static inline bool common_semi_has_synccache(CPUArchState *env)
-{
- /* Ok for A64, invalid for A32/T32. */
- return is_a64(env);
-}
-#endif /* TARGET_ARM */
-
-#ifdef TARGET_RISCV
-static inline target_ulong
-common_semi_arg(CPUState *cs, int argno)
-{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- return env->gpr[xA0 + argno];
-}
-
-static inline void
-common_semi_set_ret(CPUState *cs, target_ulong ret)
-{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- env->gpr[xA0] = ret;
-}
-
-static inline bool
-common_semi_sys_exit_extended(CPUState *cs, int nr)
-{
- return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8);
-}
-
-static inline bool is_64bit_semihosting(CPUArchState *env)
-{
- return riscv_cpu_mxl(env) != MXL_RV32;
-}
-
-static inline target_ulong common_semi_stack_bottom(CPUState *cs)
-{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- return env->gpr[xSP];
-}
-
-static inline bool common_semi_has_synccache(CPUArchState *env)
-{
- return true;
-}
-#endif
+#include "common-semi-target.h"
/*
* The semihosting API has no concept of its errno being thread-safe,
--
2.34.1
- [PULL 12/60] semihosting: Clean up common_semi_open_cb, (continued)
- [PULL 12/60] semihosting: Clean up common_semi_open_cb, Richard Henderson, 2022/06/28
- [PULL 13/60] semihosting: Return void from do_common_semihosting, Richard Henderson, 2022/06/28
- [PULL 14/60] semihosting: Move common-semi.h to include/semihosting/, Richard Henderson, 2022/06/28
- [PULL 15/60] semihosting: Remove GDB_O_BINARY, Richard Henderson, 2022/06/28
- [PULL 16/60] include/exec: Move gdb open flags to gdbstub.h, Richard Henderson, 2022/06/28
- [PULL 17/60] include/exec: Move gdb_stat and gdb_timeval to gdbstub.h, Richard Henderson, 2022/06/28
- [PULL 19/60] gdbstub: Convert GDB error numbers to host error numbers, Richard Henderson, 2022/06/28
- [PULL 22/60] semihosting: Split common_semi_flen_buf per target, Richard Henderson, 2022/06/28
- [PULL 18/60] include/exec: Define errno values in gdbstub.h, Richard Henderson, 2022/06/28
- [PULL 20/60] semihosting: Use struct gdb_stat in common_semi_flen_cb, Richard Henderson, 2022/06/28
- [PULL 24/60] semihosting: Split out common-semi-target.h,
Richard Henderson <=
- [PULL 26/60] semihosting: Move GET_ARG/SET_ARG earlier in the file, Richard Henderson, 2022/06/28
- [PULL 25/60] semihosting: Use env more often in do_common_semihosting, Richard Henderson, 2022/06/28
- [PULL 29/60] semihosting: Split out semihost_sys_read, Richard Henderson, 2022/06/28
- [PULL 21/60] semihosting: Split is_64bit_semihosting per target, Richard Henderson, 2022/06/28
- [PULL 32/60] semihosting: Split out semihost_sys_lseek, Richard Henderson, 2022/06/28
- [PULL 33/60] semihosting: Split out semihost_sys_isatty, Richard Henderson, 2022/06/28
- [PULL 28/60] semihosting: Split out semihost_sys_close, Richard Henderson, 2022/06/28
- [PULL 23/60] semihosting: Split out common_semi_has_synccache, Richard Henderson, 2022/06/28
- [PULL 30/60] semihosting: Split out semihost_sys_write, Richard Henderson, 2022/06/28
- [PULL 31/60] semihosting: Bound length for semihost_sys_{read,write}, Richard Henderson, 2022/06/28