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[PULL 21/27] hw/i2c/aspeed: Fix DMA len write-enable bit handling
From: |
Cédric Le Goater |
Subject: |
[PULL 21/27] hw/i2c/aspeed: Fix DMA len write-enable bit handling |
Date: |
Thu, 30 Jun 2022 13:24:05 +0200 |
From: Peter Delevoryas <pdel@fb.com>
I noticed i2c rx transfers were getting shortened to "1" on Zephyr. It
seems to be because the Zephyr i2c driver sets the RX DMA len with the
RX field write-enable bit set (bit 31) to avoid a read-modify-write. [1]
/* 0x1C : I2CM Master DMA Transfer Length Register */
I think we should be checking the write-enable bits on the incoming
value, not checking the register array. I'm not sure we're even writing
the write-enable bits to the register array, actually.
[1]
https://github.com/AspeedTech-BMC/zephyr/blob/db3dbcc9c52e67a47180890ac938ed380b33f91c/drivers/i2c/i2c_aspeed.c#L145-L148
Fixes: ba2cccd64e90f34 ("aspeed: i2c: Add new mode support")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220630045133.32251-3-me@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/i2c/aspeed_i2c.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 6429ab18741b..4e32b147ec2d 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -644,18 +644,18 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus,
hwaddr offset,
RX_BUF_LEN) + 1;
break;
case A_I2CM_DMA_LEN:
- w1t = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
- ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T);
+ w1t = FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
+ FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T);
/* If none of the w1t bits are set, just write to the reg as normal. */
if (!w1t) {
bus->regs[R_I2CM_DMA_LEN] = value;
break;
}
- if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) {
+ if (FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) {
ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN,
FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN));
}
- if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) {
+ if (FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) {
ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN,
FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN));
}
--
2.35.3
- [PULL 12/27] aspeed: Remove use of qemu_get_cpu, (continued)
- [PULL 12/27] aspeed: Remove use of qemu_get_cpu, Cédric Le Goater, 2022/06/30
- [PULL 11/27] aspeed: Map unimplemented devices in SoC memory, Cédric Le Goater, 2022/06/30
- [PULL 13/27] hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 board, Cédric Le Goater, 2022/06/30
- [PULL 14/27] hw/arm/aspeed: add Qualcomm Firework BMC machine, Cédric Le Goater, 2022/06/30
- [PULL 15/27] hw/i2c: pmbus: Page #255 is valid page for read requests., Cédric Le Goater, 2022/06/30
- [PULL 17/27] hw/arm/aspeed: Add MAX31785 Fan controllers, Cédric Le Goater, 2022/06/30
- [PULL 16/27] hw/sensor: add Maxim MAX31785 device, Cédric Le Goater, 2022/06/30
- [PULL 18/27] hw/arm/aspeed: firework: Add Thermal Diodes, Cédric Le Goater, 2022/06/30
- [PULL 19/27] hw/arm/aspeed: firework: add I2C MUXes for VR channels, Cédric Le Goater, 2022/06/30
- [PULL 20/27] hw/i2c/aspeed: Fix R_I2CD_FUN_CTRL reference, Cédric Le Goater, 2022/06/30
- [PULL 21/27] hw/i2c/aspeed: Fix DMA len write-enable bit handling,
Cédric Le Goater <=
- [PULL 22/27] hw/i2c/aspeed: Fix MASTER_EN missing error message, Cédric Le Goater, 2022/06/30
- [PULL 23/27] hw/i2c: support multiple masters, Cédric Le Goater, 2022/06/30
- [PULL 25/27] hw/i2c/aspeed: add slave device in old register mode, Cédric Le Goater, 2022/06/30
- [PULL 26/27] hw/i2c/aspeed: Add new-registers DMA slave mode RX support, Cédric Le Goater, 2022/06/30
- [PULL 27/27] hw/misc/aspeed: Add PECI controller, Cédric Le Goater, 2022/06/30
- [PULL 24/27] hw/i2c: add asynchronous send, Cédric Le Goater, 2022/06/30
- Re: [PULL 00/27] aspeed queue, Richard Henderson, 2022/06/30