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[PATCH 1/9] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
From: |
Bernhard Beschow |
Subject: |
[PATCH 1/9] hw/riscv/sifive_e: Fix inheritance of SiFiveEState |
Date: |
Tue, 20 Sep 2022 01:17:12 +0200 |
SiFiveEState inherits from SysBusDevice while it's TypeInfo claims it to
inherit from TYPE_MACHINE. This is an inconsistency which can cause
undefined behavior such as memory corruption.
Change SiFiveEState to inherit from MachineState since it is registered
as a machine.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
include/hw/riscv/sifive_e.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 83604da805..d738745925 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -22,6 +22,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/gpio/sifive_gpio.h"
+#include "hw/boards.h"
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
#define RISCV_E_SOC(obj) \
@@ -41,7 +42,7 @@ typedef struct SiFiveESoCState {
typedef struct SiFiveEState {
/*< private >*/
- SysBusDevice parent_obj;
+ MachineState parent_obj;
/*< public >*/
SiFiveESoCState soc;
--
2.37.3
Re: [PATCH 1/9] hw/riscv/sifive_e: Fix inheritance of SiFiveEState, Philippe Mathieu-Daudé, 2022/09/20
[PATCH 2/9] exec/hwaddr.h: Add missing include, Bernhard Beschow, 2022/09/19
[PATCH 3/9] hw/core/sysbus: Resolve main_system_bus singleton, Bernhard Beschow, 2022/09/19