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[PULL 01/12] hw/ssi: ibex_spi: fixup typos in ibex_spi_host
From: |
Alistair Francis |
Subject: |
[PULL 01/12] hw/ssi: ibex_spi: fixup typos in ibex_spi_host |
Date: |
Fri, 23 Sep 2022 14:06:53 +1000 |
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
This patch fixes up minor typos in ibex_spi_host
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-Id: <20220823061201.132342-2-wilfred.mallawa@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/ssi/ibex_spi_host.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
index d14580b409..601041d719 100644
--- a/hw/ssi/ibex_spi_host.c
+++ b/hw/ssi/ibex_spi_host.c
@@ -172,7 +172,7 @@ static void ibex_spi_host_irq(IbexSPIHostState *s)
& R_INTR_STATE_SPI_EVENT_MASK;
int err_irq = 0, event_irq = 0;
- /* Error IRQ enabled and Error IRQ Cleared*/
+ /* Error IRQ enabled and Error IRQ Cleared */
if (error_en && !err_pending) {
/* Event enabled, Interrupt Test Error */
if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) {
@@ -434,7 +434,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
case IBEX_SPI_HOST_TXDATA:
/*
* This is a hardware `feature` where
- * the first word written TXDATA after init is omitted entirely
+ * the first word written to TXDATA after init is omitted entirely
*/
if (s->init_status) {
s->init_status = false;
@@ -487,7 +487,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
break;
case IBEX_SPI_HOST_ERROR_STATUS:
/*
- * Indicates that any errors that have occurred.
+ * Indicates any errors that have occurred.
* When an error occurs, the corresponding bit must be cleared
* here before issuing any further commands
*/
--
2.37.3
- [PULL 00/12] riscv-to-apply queue, Alistair Francis, 2022/09/23
- [PULL 01/12] hw/ssi: ibex_spi: fixup typos in ibex_spi_host,
Alistair Francis <=
- [PULL 03/12] docs/system: clean up code escape for riscv virt platform, Alistair Francis, 2022/09/23
- [PULL 04/12] target/riscv: Remove sideleg and sedeleg, Alistair Francis, 2022/09/23
- [PULL 05/12] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}, Alistair Francis, 2022/09/23
- [PULL 02/12] hw/ssi: ibex_spi: update reg addr, Alistair Francis, 2022/09/23
- [PULL 10/12] hw/riscv: opentitan: Expose the resetvec as a SoC property, Alistair Francis, 2022/09/23
- [PULL 07/12] target/riscv: remove fixed numbering from GDB xml feature files, Alistair Francis, 2022/09/23
- [PULL 11/12] target/riscv: Check the correct exception cause in vector GDB stub, Alistair Francis, 2022/09/23
- [PULL 06/12] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml, Alistair Francis, 2022/09/23
- [PULL 08/12] target/riscv: Set the CPU resetvec directly, Alistair Francis, 2022/09/23
- [PULL 09/12] hw/riscv: opentitan: Fixup resetvec, Alistair Francis, 2022/09/23