Re: [PATCH v2 3/3] target/mips: Disable DSP ASE for Octeon68XX

[Pavel Dovgalyuk]

On 31.10.2022 16:25, Jiaxun Yang wrote:
> I don't have access to Octeon68XX hardware but accroading to
> my investigation Octeon never had DSP ASE support.
>
> As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
> Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
> access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 processor
> and I can confirm CP0C3_DSPP is read as 0 on that processor.
>
> Further more, in linux kernel:
> arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
> cpu_has_dsp is overridden as 0.
>
> So I believe we shouldn't emulate DSP in QEMU as well.

That's true. But there is one exception: LBX/LWX/LDX instruction.
These are grouped into DSP extension in QEMU, but Octeon supports them.
I've sent a patch for enabling these instructions.

Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>

> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Acked-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/mips/cpu-defs.c.inc | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index 7f53c94ec8..480e60aeec 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -934,7 +934,7 @@ const mips_def_t mips_defs[] =
>                          (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
>                          (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>           .CP0_Config2 = MIPS_CONFIG2,
> -        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_DSPP) ,
> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
>           .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
>                          (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
>                          (3U << CP0C4_MMUSizeExt),
> @@ -946,7 +946,7 @@ const mips_def_t mips_defs[] =
>           .CP0_Status_rw_bitmask = 0x12F8FFFF,
>           .SEGBITS = 42,
>           .PABITS = 49,
> -        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON | ASE_DSP,
> +        .insn_flags = CPU_MIPS64R2 | INSN_OCTEON,
>           .mmu_type = MMU_TYPE_R4000,
>       },
>