Re: should ioapic_service really be modelling cpu writes?

[Paolo Bonzini]

On 11/10/22 23:42, Peter Xu wrote:
> I think it shouldn't?  Normally the irq will be in MSI format (IOAPIC will
> translate to an MSI in QEMU, per ioapic_entry_parse()).
>
> I had a feeling that it'll just go the shortcut here (MSI always starts
> with 0xfeeXXXXX so definitely bigger than 0xfff):

Note that QEMU subtracts 0xfee00000 by the time you get to 
apic_mem_write, but still yes, that's what happens for IOAPIC.  The 
write is on the PCI bus.

>      if (addr > 0xfff || !index) {
>          /* MSI and MMIO APIC are at the same memory location,
>           * but actually not on the global bus: MSI is on PCI bus
>           * APIC is connected directly to the CPU.
>           * Mapping them on the global bus happens to work because
>           * MSI registers are reserved in APIC MMIO and vice versa. */
>          MSIMessage msi = { .address = addr, .data = val };
>          apic_send_msi(&msi);
>          return;
>      }
>
> apic_send_msi() doesn't need a cpu context.

Alex, perhaps you can change the shortcut to

    if (size < 4) {
        return;
    }

    dev = cpu_get_current_apic(memtxattrs);
    if (!dev) {
        /* comment here... */
        MSIMessage msi = { .address = addr, .data = val };
        apic_send_msi(&msi);
        return;
    }

    s = APIC(dev);
    ...

Paolo