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[PATCH v3 03/34] tcg/s390x: Fix coding style
From: |
Richard Henderson |
Subject: |
[PATCH v3 03/34] tcg/s390x: Fix coding style |
Date: |
Thu, 1 Dec 2022 21:39:27 -0800 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
We are going to modify this code, so fix its style first to avoid:
ERROR: spaces required around that '*' (ctx:VxV)
#281: FILE: tcg/s390x/tcg-target.c.inc:1224:
+ uintptr_t mask = ~(0xffffull << i*16);
^
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221130132654.76369-2-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.c.inc | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 33becd7694..f1d3907cd8 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -802,9 +802,9 @@ static bool maybe_out_small_movi(TCGContext *s, TCGType
type,
}
for (i = 0; i < 4; i++) {
- tcg_target_long mask = 0xffffull << i*16;
+ tcg_target_long mask = 0xffffull << i * 16;
if ((uval & mask) == uval) {
- tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);
+ tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i * 16);
return true;
}
}
@@ -1221,9 +1221,9 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg
dest, uint64_t val)
/* Try all 32-bit insns that can perform it in one go. */
for (i = 0; i < 4; i++) {
- tcg_target_ulong mask = ~(0xffffull << i*16);
+ tcg_target_ulong mask = ~(0xffffull << i * 16);
if (((val | ~valid) & mask) == mask) {
- tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
+ tcg_out_insn_RI(s, ni_insns[i], dest, val >> i * 16);
return;
}
}
@@ -1231,9 +1231,9 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg
dest, uint64_t val)
/* Try all 48-bit insns that can perform it in one go. */
if (HAVE_FACILITY(EXT_IMM)) {
for (i = 0; i < 2; i++) {
- tcg_target_ulong mask = ~(0xffffffffull << i*32);
+ tcg_target_ulong mask = ~(0xffffffffull << i * 32);
if (((val | ~valid) & mask) == mask) {
- tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
+ tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i * 32);
return;
}
}
@@ -1279,9 +1279,9 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg
dest, uint64_t val)
/* Try all 32-bit insns that can perform it in one go. */
for (i = 0; i < 4; i++) {
- tcg_target_ulong mask = (0xffffull << i*16);
+ tcg_target_ulong mask = (0xffffull << i * 16);
if ((val & mask) != 0 && (val & ~mask) == 0) {
- tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
+ tcg_out_insn_RI(s, oi_insns[i], dest, val >> i * 16);
return;
}
}
@@ -1289,9 +1289,9 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg
dest, uint64_t val)
/* Try all 48-bit insns that can perform it in one go. */
if (HAVE_FACILITY(EXT_IMM)) {
for (i = 0; i < 2; i++) {
- tcg_target_ulong mask = (0xffffffffull << i*32);
+ tcg_target_ulong mask = (0xffffffffull << i * 32);
if ((val & mask) != 0 && (val & ~mask) == 0) {
- tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32);
+ tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i * 32);
return;
}
}
--
2.34.1
- [PATCH for-8.0 v3 00/34] tcg misc patches, Richard Henderson, 2022/12/02
- [PATCH v3 02/34] meson: Move CONFIG_TCG_INTERPRETER to config_host, Richard Henderson, 2022/12/02
- [PATCH v3 03/34] tcg/s390x: Fix coding style,
Richard Henderson <=
- [PATCH v3 04/34] tcg: Cleanup trailing whitespace, Richard Henderson, 2022/12/02
- [PATCH v3 05/34] tcg: Fix tcg_reg_alloc_dup*, Richard Henderson, 2022/12/02
- [PATCH v3 06/34] tcg: Centralize updates to reg_to_temp, Richard Henderson, 2022/12/02
- [PATCH v3 01/34] tcg: convert tcg/README to rst, Richard Henderson, 2022/12/02
- [PATCH v3 07/34] tcg: Remove check_regs, Richard Henderson, 2022/12/02
- [PATCH v3 10/34] tcg: Remove TCG_TARGET_STACK_GROWSUP, Richard Henderson, 2022/12/02
- [PATCH v3 09/34] tcg: Introduce paired register allocation, Richard Henderson, 2022/12/02
- [PATCH v3 11/34] accel/tcg: Set cflags_next_tb in cpu_common_initfn, Richard Henderson, 2022/12/02
- [PATCH v3 08/34] tcg: Tidy tcg_reg_alloc_op, Richard Henderson, 2022/12/02