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[PATCH v3 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt c
From: |
Bin Meng |
Subject: |
[PATCH v3 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers |
Date: |
Sun, 11 Dec 2022 11:08:15 +0800 |
hw/pci/Kconfig says MSI_NONBROKEN should be selected by interrupt
controllers regardless of how MSI is implemented. msi_nonbroken is
initialized to true in both riscv_aplic_realize() and
riscv_imsic_realize().
Select MSI_NONBROKEN in RISCV_APLIC and RISCV_IMSIC.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
(no changes since v1)
hw/intc/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 1d4573e803..21441d0a0c 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -72,9 +72,11 @@ config RISCV_ACLINT
config RISCV_APLIC
bool
+ select MSI_NONBROKEN
config RISCV_IMSIC
bool
+ select MSI_NONBROKEN
config SIFIVE_PLIC
bool
--
2.34.1
- [PATCH v3 01/16] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Bin Meng, 2022/12/10
- [PATCH v3 02/16] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers,
Bin Meng <=
- [PATCH v3 04/16] hw/riscv: Sort machines Kconfig options in alphabetical order, Bin Meng, 2022/12/10
- [PATCH v3 03/16] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Bin Meng, 2022/12/10
- [PATCH v3 05/16] hw/riscv: spike: Remove misleading comments, Bin Meng, 2022/12/10
- [PATCH v3 06/16] hw/intc: sifive_plic: Drop PLICMode_H, Bin Meng, 2022/12/10
- [PATCH v3 07/16] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Bin Meng, 2022/12/10
- [PATCH v3 08/16] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), Bin Meng, 2022/12/10
- [PATCH v3 09/16] hw/intc: sifive_plic: Update "num-sources" property default value, Bin Meng, 2022/12/10
- [PATCH v3 11/16] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/10
- [PATCH v3 12/16] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Bin Meng, 2022/12/10
- [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/10