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[PULL 10/21] Hexagon (target/hexagon) Use direct block chaining for dire
From: |
Taylor Simpson |
Subject: |
[PULL 10/21] Hexagon (target/hexagon) Use direct block chaining for direct jump/branch |
Date: |
Fri, 16 Dec 2022 12:48:34 -0800 |
Direct block chaining is documented here
https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining
Recall that Hexagon allows packets with multiple jumps where only the
first one with a true predicate will actually jump. We can use
tcg_gen_goto_tb/tcg_gen_exit_tb when the packet contains a single
PC-relative branch or jump. If not, we use tcg_gen_lookup_and_goto_ptr.
We add the following to DisasContext in order to delay the branching
until the end of packet commit (in gen_end_tb)
branch_cond
The TCGCond condition under which the branch is taken
When branch_cond == TCG_COND_NEVER, there isn't a single
direct branch in this packet.
When branch_cond != TCG_COND_ALWAYS, the value is in
hex_branch_taken
branch_dest
The destination of the branch
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20221108162906.3166-11-tsimpson@quicinc.com>
---
target/hexagon/translate.h | 2 ++
target/hexagon/genptr.c | 12 +++++++++++-
target/hexagon/translate.c | 34 +++++++++++++++++++++++++++++++++-
3 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 96509a4da7..aacf0b0921 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -57,6 +57,8 @@ typedef struct DisasContext {
bool qreg_is_predicated[NUM_QREGS];
int qreg_log_idx;
bool pre_commit;
+ TCGCond branch_cond;
+ target_ulong branch_dest;
} DisasContext;
static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index be9c715ea8..ee0f86fab2 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -484,7 +484,17 @@ static void gen_write_new_pc_pcrel(DisasContext *ctx, int
pc_off,
TCGCond cond, TCGv pred)
{
target_ulong dest = ctx->pkt->pc + pc_off;
- gen_write_new_pc_addr(ctx, tcg_constant_tl(dest), cond, pred);
+ if (ctx->pkt->pkt_has_multi_cof) {
+ gen_write_new_pc_addr(ctx, tcg_constant_tl(dest), cond, pred);
+ } else {
+ /* Defer this jump to the end of the TB */
+ ctx->branch_cond = TCG_COND_ALWAYS;
+ if (pred != NULL) {
+ ctx->branch_cond = cond;
+ tcg_gen_mov_tl(hex_branch_taken, pred);
+ }
+ ctx->branch_dest = dest;
+ }
}
static void gen_compare(TCGCond cond, TCGv res, TCGv arg1, TCGv arg2)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index fa6415936c..f5ef54f039 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -116,10 +116,41 @@ static void gen_exec_counters(DisasContext *ctx)
hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns);
}
+static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
+{
+ return translator_use_goto_tb(&ctx->base, dest);
+}
+
+static void gen_goto_tb(DisasContext *ctx, int idx, target_ulong dest)
+{
+ if (use_goto_tb(ctx, dest)) {
+ tcg_gen_goto_tb(idx);
+ tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
+ tcg_gen_exit_tb(ctx->base.tb, idx);
+ } else {
+ tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], dest);
+ tcg_gen_lookup_and_goto_ptr();
+ }
+}
+
static void gen_end_tb(DisasContext *ctx)
{
gen_exec_counters(ctx);
- tcg_gen_exit_tb(NULL, 0);
+
+ if (ctx->branch_cond != TCG_COND_NEVER) {
+ if (ctx->branch_cond != TCG_COND_ALWAYS) {
+ TCGLabel *skip = gen_new_label();
+ tcg_gen_brcondi_tl(ctx->branch_cond, hex_branch_taken, 0, skip);
+ gen_goto_tb(ctx, 0, ctx->branch_dest);
+ gen_set_label(skip);
+ gen_goto_tb(ctx, 1, ctx->next_PC);
+ } else {
+ gen_goto_tb(ctx, 0, ctx->branch_dest);
+ }
+ } else {
+ tcg_gen_lookup_and_goto_ptr();
+ }
+
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -807,6 +838,7 @@ static void hexagon_tr_init_disas_context(DisasContextBase
*dcbase,
ctx->num_packets = 0;
ctx->num_insns = 0;
ctx->num_hvx_insns = 0;
+ ctx->branch_cond = TCG_COND_NEVER;
}
static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)
--
2.17.1
- [PULL 00/21] Hexagon update: bug fixes, performance, idef-parser, Taylor Simpson, 2022/12/16
- [PULL 11/21] Hexagon (target/hexagon) Use direct block chaining for tight loops, Taylor Simpson, 2022/12/16
- [PULL 14/21] target/hexagon: make slot number an unsigned, Taylor Simpson, 2022/12/16
- [PULL 06/21] Hexagon (target/hexagon) Remove next_PC from runtime state, Taylor Simpson, 2022/12/16
- [PULL 02/21] Hexagon (target/hexagon) Fix predicated assignment to .tmp and .cur, Taylor Simpson, 2022/12/16
- [PULL 07/21] Hexagon (target/hexagon) Add overrides for direct call instructions, Taylor Simpson, 2022/12/16
- [PULL 01/21] Hexagon (target/hexagon) Add pkt and insn to DisasContext, Taylor Simpson, 2022/12/16
- [PULL 04/21] Hexagon (target/hexagon) Only use branch_taken when packet has multi cof, Taylor Simpson, 2022/12/16
- [PULL 10/21] Hexagon (target/hexagon) Use direct block chaining for direct jump/branch,
Taylor Simpson <=
- [PULL 03/21] Hexagon (target/hexagon) Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat, Taylor Simpson, 2022/12/16
- [PULL 08/21] Hexagon (target/hexagon) Add overrides for compound compare and jump, Taylor Simpson, 2022/12/16
- [PULL 05/21] Hexagon (target/hexagon) Remove PC from the runtime state, Taylor Simpson, 2022/12/16
- [PULL 12/21] target/hexagon: update MAINTAINERS for idef-parser, Taylor Simpson, 2022/12/16
- [PULL 20/21] target/hexagon: call idef-parser functions, Taylor Simpson, 2022/12/16
- [PULL 09/21] Hexagon (target/hexagon) Add overrides for various forms of jump, Taylor Simpson, 2022/12/16
- [PULL 16/21] target/hexagon: introduce new helper functions, Taylor Simpson, 2022/12/16
- [PULL 18/21] target/hexagon: import lexer for idef-parser, Taylor Simpson, 2022/12/16
- [PULL 17/21] target/hexagon: prepare input for the idef-parser, Taylor Simpson, 2022/12/16