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[PULL 33/36] pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phas
From: |
Peter Maydell |
Subject: |
[PULL 33/36] pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset |
Date: |
Fri, 16 Dec 2022 21:42:41 +0000 |
Convert the TYPE_CXL_ROOT_PORT and TYPE_PNV_PHB_ROOT_PORT classes to
3-phase reset, so they don't need to use the deprecated
device_class_set_parent_reset() function any more.
We have to do both in the same commit, because they keep the
parent_reset field in their common parent class's class struct.
Note that pnv_phb_root_port_class_init() was pointlessly setting
dc->reset twice, once by calling device_class_set_parent_reset()
and once directly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221125115240.3005559-5-peter.maydell@linaro.org
---
include/hw/pci/pcie_port.h | 2 +-
hw/pci-bridge/cxl_root_port.c | 14 +++++++++-----
hw/pci-host/pnv_phb.c | 18 ++++++++++--------
3 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h
index 7b8193061ac..d9b5d075049 100644
--- a/include/hw/pci/pcie_port.h
+++ b/include/hw/pci/pcie_port.h
@@ -80,7 +80,7 @@ DECLARE_CLASS_CHECKERS(PCIERootPortClass, PCIE_ROOT_PORT,
struct PCIERootPortClass {
PCIDeviceClass parent_class;
DeviceRealize parent_realize;
- DeviceReset parent_reset;
+ ResettablePhases parent_phases;
uint8_t (*aer_vector)(const PCIDevice *dev);
int (*interrupts_init)(PCIDevice *dev, Error **errp);
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index fb213fa06ef..6664783974c 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -138,12 +138,14 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp)
component_bar);
}
-static void cxl_rp_reset(DeviceState *dev)
+static void cxl_rp_reset_hold(Object *obj)
{
- PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
- CXLRootPort *crp = CXL_ROOT_PORT(dev);
+ PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
+ CXLRootPort *crp = CXL_ROOT_PORT(obj);
- rpc->parent_reset(dev);
+ if (rpc->parent_phases.hold) {
+ rpc->parent_phases.hold(obj);
+ }
latch_registers(crp);
}
@@ -199,6 +201,7 @@ static void cxl_root_port_class_init(ObjectClass *oc, void
*data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PCIDeviceClass *k = PCI_DEVICE_CLASS(oc);
+ ResettableClass *rc = RESETTABLE_CLASS(oc);
PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc);
k->vendor_id = PCI_VENDOR_ID_INTEL;
@@ -209,7 +212,8 @@ static void cxl_root_port_class_init(ObjectClass *oc, void
*data)
k->config_write = cxl_rp_write_config;
device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize);
- device_class_set_parent_reset(dc, cxl_rp_reset, &rpc->parent_reset);
+ resettable_class_set_parent_phases(rc, NULL, cxl_rp_reset_hold, NULL,
+ &rpc->parent_phases);
rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c
index 0b26b43736f..c62b08538ac 100644
--- a/hw/pci-host/pnv_phb.c
+++ b/hw/pci-host/pnv_phb.c
@@ -199,14 +199,16 @@ static void pnv_phb_class_init(ObjectClass *klass, void
*data)
dc->user_creatable = true;
}
-static void pnv_phb_root_port_reset(DeviceState *dev)
+static void pnv_phb_root_port_reset_hold(Object *obj)
{
- PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
- PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(dev);
- PCIDevice *d = PCI_DEVICE(dev);
+ PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
+ PnvPHBRootPort *phb_rp = PNV_PHB_ROOT_PORT(obj);
+ PCIDevice *d = PCI_DEVICE(obj);
uint8_t *conf = d->config;
- rpc->parent_reset(dev);
+ if (rpc->parent_phases.hold) {
+ rpc->parent_phases.hold(obj);
+ }
if (phb_rp->version == 3) {
return;
@@ -300,6 +302,7 @@ static Property pnv_phb_root_port_properties[] = {
static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
@@ -308,9 +311,8 @@ static void pnv_phb_root_port_class_init(ObjectClass
*klass, void *data)
device_class_set_props(dc, pnv_phb_root_port_properties);
device_class_set_parent_realize(dc, pnv_phb_root_port_realize,
&rpc->parent_realize);
- device_class_set_parent_reset(dc, pnv_phb_root_port_reset,
- &rpc->parent_reset);
- dc->reset = &pnv_phb_root_port_reset;
+ resettable_class_set_parent_phases(rc, NULL, pnv_phb_root_port_reset_hold,
+ NULL, &rpc->parent_phases);
dc->user_creatable = true;
k->vendor_id = PCI_VENDOR_ID_IBM;
--
2.25.1
- [PULL 11/36] hw/core/cpu-common: Convert TYPE_CPU class to 3-phase reset, (continued)
- [PULL 11/36] hw/core/cpu-common: Convert TYPE_CPU class to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 15/36] target/hexagon: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 16/36] target/i386: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 17/36] target/loongarch: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 18/36] target/m68k: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 21/36] target/nios2: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 25/36] target/rx: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 24/36] target/riscv: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 26/36] target/sh4: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 32/36] pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 33/36] pci: Convert child classes of TYPE_PCIE_ROOT_PORT to 3-phase reset,
Peter Maydell <=
- [PULL 23/36] target/ppc: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 27/36] target/sparc: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 29/36] target/xtensa: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 35/36] hw/intc/xics: Convert TYPE_ICS to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 30/36] hw/virtio: Convert TYPE_VIRTIO_PCI to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 28/36] target/tricore: Convert to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 31/36] hw/display/virtio-vga: Convert TYPE_VIRTIO_VGA_BASE to 3-phase reset, Peter Maydell, 2022/12/16
- [PULL 34/36] hw/intc/xics: Reset TYPE_ICS objects with device_cold_reset(), Peter Maydell, 2022/12/16
- [PULL 36/36] hw/pci-host/pnv_phb3_msi: Convert TYPE_PHB3_MSI to 3-phase reset, Peter Maydell, 2022/12/16
- Re: [PULL 00/36] reset refactoring patches, Peter Maydell, 2022/12/17