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[PULL 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12
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From: |
Alistair Francis |
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Subject: |
[PULL 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 |
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Date: |
Mon, 19 Dec 2022 12:16:22 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
We were matching a signed 13-bit range, not a 12-bit range.
Expand the commentary within the function and be explicit
about all of the ranges.
Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221022095821.2441874-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 81a83e45b1..191197853f 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType
type, int ct)
if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return 1;
}
- if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
+ /*
+ * Sign extended from 12 bits: [-0x800, 0x7ff].
+ * Used for most arithmetic, as this is the isa field.
+ */
+ if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) {
return 1;
}
- if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
+ /*
+ * Sign extended from 12 bits, negated: [-0x7ff, 0x800].
+ * Used for subtraction, where a constant must be handled by ADDI.
+ */
+ if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) {
return 1;
}
- if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
+ /*
+ * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff].
+ * Used by addsub2, which may need the negative operation,
+ * and requires the modified constant to be representable.
+ */
+ if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) {
return 1;
}
return 0;
--
2.38.1
- [PULL 00/45] riscv-to-apply queue, Alistair Francis, 2022/12/18
- [PULL 01/45] target/riscv: Fix PMP propagation for tlb, Alistair Francis, 2022/12/18
- [PULL 02/45] hw/registerfields: add `FIELDx_1CLEAR()` macro, Alistair Francis, 2022/12/18
- [PULL 03/45] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro, Alistair Francis, 2022/12/18
- [PULL 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2, Alistair Francis, 2022/12/18
- [PULL 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12,
Alistair Francis <=
- [PULL 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st, Alistair Francis, 2022/12/18
- [PULL 07/45] hw/riscv/opentitan: bump opentitan, Alistair Francis, 2022/12/18
- [PULL 08/45] hw/riscv/opentitan: add aon_timer base unimpl, Alistair Francis, 2022/12/18
- [PULL 09/45] target/riscv: Add smstateen support, Alistair Francis, 2022/12/18
- [PULL 10/45] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2022/12/18
- [PULL 11/45] target/riscv: generate virtual instruction exception, Alistair Francis, 2022/12/18
- [PULL 12/45] target/riscv: Add itrigger support when icount is not enabled, Alistair Francis, 2022/12/18
- [PULL 13/45] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2022/12/18
- [PULL 14/45] target/riscv: Enable native debug itrigger, Alistair Francis, 2022/12/18
- [PULL 15/45] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2022/12/18