[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PULL 00/45] riscv-to-apply queue
|
From: |
Peter Maydell |
|
Subject: |
Re: [PULL 00/45] riscv-to-apply queue |
|
Date: |
Tue, 20 Dec 2022 15:32:08 +0000 |
On Mon, 19 Dec 2022 at 23:29, Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Dec 20, 2022 at 1:12 AM Peter Maydell <peter.maydell@linaro.org>
> wrote:
> >
> > On Mon, 19 Dec 2022 at 02:29, Alistair Francis
> > <alistair.francis@opensource.wdc.com> wrote:
> > >
> > > From: Alistair Francis <alistair.francis@wdc.com>
> > >
> > > The following changes since commit
> > > 562d4af32ec2213061f844b3838223fd7711b56a:
> > >
> > > Merge tag 'pull-loongarch-20221215' of https://gitlab.com/gaosong/qemu
> > > into staging (2022-12-18 13:53:29 +0000)
> > >
> > > are available in the Git repository at:
> > >
> > > https://github.com/alistair23/qemu.git
> > > tags/pull-riscv-to-apply-20221219-3
> > >
> > > for you to fetch changes up to e59b3c6ece6a1351aeca6b916cd9674e23d15e89:
> > >
> > > hw/intc: sifive_plic: Fix the pending register range check (2022-12-19
> > > 10:42:14 +1000)
> > >
> > > ----------------------------------------------------------------
> > > First RISC-V PR for QEMU 8.0
> > >
> > > * Fix PMP propagation for tlb
> > > * Collection of bug fixes
> > > * Add the `FIELDx_1CLEAR()` macro
> > > * Bump the OpenTitan supported version
> > > * Add smstateen support
> > > * Support native debug icount trigger
> > > * Remove the redundant ipi-id property in the virt machine
> > > * Support cache-related PMU events in virtual mode
> > > * Add some missing PolarFire SoC io regions
> > > * Fix mret exception cause when no pmp rule is configured
> > > * Fix bug where disabling compressed instructions would crash QEMU
> > > * Add Zawrs ISA extension support
> > > * A range of code refactoring and cleanups
> >
> > Hi -- gpg says your key expired last week. What keyserver can I
> > download the updated key from, please ?
>
> Sorry about that.
>
> You should be able to get a valid key from:
>
> https://keys.openpgp.org/search?q=F6C4AC46D4934868D3B8CE8F21E10D29DF977054
Thanks. The pullreq seems to fail in 'make check-tcg' for the linux-user
tests:
TEST test-noc-with-libbb.so on riscv64
make[1]: *** [Makefile:173: run-plugin-test-noc-with-libbb.so] Error 1
make: *** [/builds/qemu-project/qemu/tests/Makefile.include:56:
run-tcg-tests-riscv64-linux-user] Error 2
https://gitlab.com/qemu-project/qemu/-/jobs/3502502318
thanks
-- PMM
- [PULL 38/45] hw/intc: sifive_plic: Update "num-sources" property default value, (continued)
- [PULL 38/45] hw/intc: sifive_plic: Update "num-sources" property default value, Alistair Francis, 2022/12/18
- [PULL 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Alistair Francis, 2022/12/18
- [PULL 40/45] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Alistair Francis, 2022/12/18
- [PULL 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Alistair Francis, 2022/12/18
- [PULL 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Alistair Francis, 2022/12/18
- [PULL 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Alistair Francis, 2022/12/18
- [PULL 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Alistair Francis, 2022/12/18
- [PULL 45/45] hw/intc: sifive_plic: Fix the pending register range check, Alistair Francis, 2022/12/18
- Re: [PULL 00/45] riscv-to-apply queue, Peter Maydell, 2022/12/19