[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: [PATCH v2] Hexagon (target/hexagon) implement mutability mask for GP
From: |
Taylor Simpson |
Subject: |
RE: [PATCH v2] Hexagon (target/hexagon) implement mutability mask for GPRs |
Date: |
Wed, 21 Dec 2022 20:06:22 +0000 |
> -----Original Message-----
> From: Marco Liebel <mliebel@qti.qualcomm.com>
> Sent: Wednesday, December 21, 2022 1:34 PM
> To: Taylor Simpson <tsimpson@quicinc.com>; Marco Liebel (QUIC)
> <quic_mliebel@quicinc.com>; qemu-devel@nongnu.org
> Cc: Brian Cain <bcain@quicinc.com>
> Subject: RE: [PATCH v2] Hexagon (target/hexagon) implement mutability
> mask for GPRs
>
> > > +#define WRITE_REG_IN_PACKET(reg_name, output, input) \
> > > + asm volatile("{ " reg_name " = %1 }\n\t" \
> >
> > This is no different from the WRITE_REG above. Instructions on a line
> > with no curly braces are a single packet.
> >
>
> Understood. The feedback on Brian's patch said to write tests that do
> transfers in a packet. Should I write some? (Just not in the way I did it
> above)
Put some more instructions in the packet with the assignment. I recommend a
read from the same register and verify you get the old value.
>
> > > +
> > > +/*
> > > + * Instruction word: { pc = r0 }
> > > + *
> > > + * This instruction is barred by the assembler.
> > > + *
> > > + * 3 2 1
> > > + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> > > + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> > > + * | Opc[A2_tfrrcr] | Src[R0] |P P| | C9/PC |
> > > + *
> > > ++-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> > > + */
> > > +#define PC_EQ_R0 ".word 0x6220c009\n\t"
> > > +#define GP_EQ_R0 ".word 0x6220c00b\n\t"
> > > +#define UPCYCLELO_EQ_R0 ".word 0x6220c00e\n\t"
> > > +#define UPCYCLEHI_EQ_R0 ".word 0x6220c00f\n\t"
> > > +#define UTIMERLO_EQ_R0 ".word 0x6220c01e\n\t"
> > > +#define UTIMERHI_EQ_R0 ".word 0x6220c01f\n\t"
> > > +
> > > +#define C9_8_EQ_R1_0 ".word 0x6320c008\n\t"
> > > +#define C11_10_EQ_R1_0 ".word 0x6320c00a\n\t"
> > > +#define C15_14_EQ_R1_0 ".word 0x6320c00e\n\t"
> > > +#define C31_30_EQ_R1_0 ".word 0x6320c01e\n\t"
> >
> > Only the assignment to PC and C9 (which is an alias for PC) are not
> > allowed by the assembler. For the others, use the normal assembly syntax.
> >
>
> I used the regular names at first, but when running `make check-tcg` it
> generates errors. For example:
> error: unknown register name 'gp' in asm WRITE_REG(result, "gp",
> 0xffffffff);
>
> Should I use them anyway?
Don't use the WRITE_REG macro because that puts reg_name in the clobbers list
and the compiler doesn't know about these registers. If you use the
WRITE_REG_ENCODED macro, it should work - though you might want to change the
name of the macro to WRITE_REG_NOCLOBBER.
Thanks,
Taylor