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[PULL v2 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dt
From: |
Alistair Francis |
Subject: |
[PULL v2 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb |
Date: |
Thu, 22 Dec 2022 08:40:19 +1000 |
From: Bin Meng <bmeng@tinylab.org>
Commit 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt
machine")
changed the value of VIRT_IRQCHIP_NUM_SOURCES from 127 to 53, which
is VIRTIO_NDEV and also used as the value of "riscv,ndev" property
in the dtb. Unfortunately this is wrong as VIRT_IRQCHIP_NUM_SOURCES
should include interrupt source 0 but "riscv,ndev" does not.
While we are here, we also fix the comments of platform bus irq range
which is now "64 to 96", but should be "64 to 95", introduced since
commit 1832b7cb3f64 ("hw/riscv: virt: Create a platform bus").
Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt
machine")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-13-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/virt.h | 5 ++---
hw/riscv/virt.c | 3 ++-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 62513e075c..e1ce0048af 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -87,14 +87,13 @@ enum {
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
PCIE_IRQ = 0x20, /* 32 to 35 */
- VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 96 */
- VIRTIO_NDEV = 96 /* Arbitrary maximum number of interrupts */
+ VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */
};
#define VIRT_PLATFORM_BUS_NUM_IRQS 32
#define VIRT_IRQCHIP_NUM_MSIS 255
-#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV
+#define VIRT_IRQCHIP_NUM_SOURCES 96
#define VIRT_IRQCHIP_NUM_PRIO_BITS 3
#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3
#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6cf9355b99..94ff2a1584 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -468,7 +468,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
- qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
+ qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev",
+ VIRT_IRQCHIP_NUM_SOURCES - 1);
riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
plic_phandles[socket]);
--
2.38.1
- [PULL v2 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers, (continued)
- [PULL v2 31/45] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers, Alistair Francis, 2022/12/21
- [PULL v2 32/45] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC, Alistair Francis, 2022/12/21
- [PULL v2 33/45] hw/riscv: Sort machines Kconfig options in alphabetical order, Alistair Francis, 2022/12/21
- [PULL v2 35/45] hw/intc: sifive_plic: Drop PLICMode_H, Alistair Francis, 2022/12/21
- [PULL v2 36/45] hw/intc: sifive_plic: Improve robustness of the PLIC config parser, Alistair Francis, 2022/12/21
- [PULL v2 34/45] hw/riscv: spike: Remove misleading comments, Alistair Francis, 2022/12/21
- [PULL v2 37/45] hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize(), Alistair Francis, 2022/12/21
- [PULL v2 38/45] hw/intc: sifive_plic: Update "num-sources" property default value, Alistair Francis, 2022/12/21
- [PULL v2 39/45] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC, Alistair Francis, 2022/12/21
- [PULL v2 40/45] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Alistair Francis, 2022/12/21
- [PULL v2 42/45] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb,
Alistair Francis <=
- [PULL v2 41/45] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", Alistair Francis, 2022/12/21
- [PULL v2 43/45] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Alistair Francis, 2022/12/21
- [PULL v2 44/45] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Alistair Francis, 2022/12/21
- [PULL v2 45/45] hw/intc: sifive_plic: Fix the pending register range check, Alistair Francis, 2022/12/21