RE: [PATCH 2/2] target/hexagon: rename aliased register HEX_REG_P3_0

[Mukilan Thiyagarajan (QUIC)]

> Not sure why you broke this comment into two lines, but ...

I'm not sure if this issue is on my end or your mail client, but the 
formatting appears to be correct in the patchew:
https://patchew.org/QEMU/20221227153447.2729-1-quic._5Fmthiyaga@quicinc.com/20221227153447.2729-3-quic._5Fmthiyaga@quicinc.com/

Please let me know if the formatting is still off in v2 of the patch for you.

Thanks,
Mukilan

-----Original Message-----
From: Taylor Simpson <tsimpson@quicinc.com> 
Sent: Wednesday, December 28, 2022 11:35 PM
To: Mukilan Thiyagarajan (QUIC) <quic_mthiyaga@quicinc.com>; 
qemu-devel@nongnu.org; laurent@vivier.eu
Cc: Brian Cain <bcain@quicinc.com>; richard.henderson@linaro.org; 
alex.bennee@linaro.org
Subject: RE: [PATCH 2/2] target/hexagon: rename aliased register HEX_REG_P3_0



> -----Original Message-----
> From: Mukilan Thiyagarajan (QUIC) <quic_mthiyaga@quicinc.com>
> Sent: Tuesday, December 27, 2022 9:35 AM
> To: qemu-devel@nongnu.org; Taylor Simpson <tsimpson@quicinc.com>; 
> laurent@vivier.eu
> Cc: Brian Cain <bcain@quicinc.com>; richard.henderson@linaro.org; 
> alex.bennee@linaro.org; Mukilan Thiyagarajan (QUIC) 
> <quic_mthiyaga@quicinc.com>
> Subject: [PATCH 2/2] target/hexagon: rename aliased register
> HEX_REG_P3_0
> 
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index
> 658ca4ff78..807037c586 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -86,7 +86,7 @@ static target_ulong 
> adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
>      return addr;
>  }
> 
> -/* HEX_REG_P3_0 (aka C4) is an alias for the predicate registers */
> +/* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate 
> +registers */

Not sure why you broke this comment into two lines, but ...
/*
 * Multiline comments should be
 * formatted like this
 */

Otherwise
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>