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[PATCH v3 4/8] target/tricore: Add crc32l.w insn
From: |
Bastian Koppelmann |
Subject: |
[PATCH v3 4/8] target/tricore: Add crc32l.w insn |
Date: |
Wed, 14 Jun 2023 12:00:35 +0200 |
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/helper.h | 3 ++-
target/tricore/op_helper.c | 10 +++++++++-
target/tricore/translate.c | 12 ++++++++++--
target/tricore/tricore-opcodes.h | 3 ++-
4 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index b64780c37d..24da5e97c0 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -131,7 +131,8 @@ DEF_HELPER_FLAGS_5(mul_h, TCG_CALL_NO_RWG_SE, i64, i32,
i32, i32, i32, i32)
DEF_HELPER_FLAGS_5(mulm_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
/* crc32 */
-DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
/* CSA */
DEF_HELPER_2(call, void, env, i32)
DEF_HELPER_1(ret, void, env)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 54f54811d9..8ce404cb93 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2284,7 +2284,7 @@ uint32_t helper_mulr_h(uint32_t arg00, uint32_t arg01,
return (result1 & 0xffff0000) | (result0 >> 16);
}
-uint32_t helper_crc32(uint32_t arg0, uint32_t arg1)
+uint32_t helper_crc32_be(uint32_t arg0, uint32_t arg1)
{
uint8_t buf[4];
stl_be_p(buf, arg0);
@@ -2292,6 +2292,14 @@ uint32_t helper_crc32(uint32_t arg0, uint32_t arg1)
return crc32(arg1, buf, 4);
}
+uint32_t helper_crc32_le(uint32_t arg0, uint32_t arg1)
+{
+ uint8_t buf[4];
+ stl_le_p(buf, arg0);
+
+ return crc32(arg1, buf, 4);
+}
+
/* context save area (CSA) related helpers */
static int cdc_increment(target_ulong *psw)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 898557d22a..250de80de5 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6190,13 +6190,21 @@ static void decode_rr_divide(DisasContext *ctx)
CHECK_REG_PAIR(r3);
gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
break;
- case OPC2_32_RR_CRC32:
+ case OPC2_32_RR_CRC32: /* CRC32B.W in 1.6.2 */
if (has_feature(ctx, TRICORE_FEATURE_161)) {
- gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ gen_helper_crc32_be(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
break;
+ case OPC2_32_RR_CRC32L_W:
+ if (has_feature(ctx, TRICORE_FEATURE_162)) {
+ gen_helper_crc32_le(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
+ break;
+
case OPC2_32_RR_POPCNT_W:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
tcg_gen_ctpop_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 9fab4bd75c..be07f82ec1 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1139,7 +1139,8 @@ enum {
OPC2_32_RR_DVINIT_U = 0x0a,
OPC2_32_RR_PARITY = 0x02,
OPC2_32_RR_UNPACK = 0x08,
- OPC2_32_RR_CRC32 = 0x03,
+ OPC2_32_RR_CRC32 = 0x03, /* CRC32B.W in 1.6.2
*/
+ OPC2_32_RR_CRC32L_W = 0x07, /* 1.6.2 only */
OPC2_32_RR_POPCNT_W = 0x22, /* 1.6.2 only */
OPC2_32_RR_DIV = 0x20,
OPC2_32_RR_DIV_U = 0x21,
--
2.40.1
- [PATCH v3 0/8] TriCore 1.6.2 Instructions, Bastian Koppelmann, 2023/06/14
- [PATCH v3 1/8] target/tricore: Introduce ISA 1.6.2 feature, Bastian Koppelmann, 2023/06/14
- [PATCH v3 2/8] target/tricore: Add popcnt.w insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 3/8] target/tricore: Add LHA insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 4/8] target/tricore: Add crc32l.w insn,
Bastian Koppelmann <=
- [PATCH v3 5/8] target/tricore: Add crc32.b insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 6/8] target/tricore: Add shuffle insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 7/8] target/tricore: Implement SYCSCALL insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 8/8] target/tricore: Add DISABLE insn variant, Bastian Koppelmann, 2023/06/14