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[PULL 02/33] target/arm: Return correct result for LDG when ATA=0
From: |
Peter Maydell |
Subject: |
[PULL 02/33] target/arm: Return correct result for LDG when ATA=0 |
Date: |
Mon, 19 Jun 2023 15:28:43 +0100 |
The LDG instruction loads the tag from a memory address (identified
by [Xn + offset]), and then merges that tag into the destination
register Xt. We implemented this correctly for the case when
allocation tags are enabled, but didn't get it right when ATA=0:
instead of merging the tag bits into Xt, we merged them into the
memory address [Xn + offset] and then set Xt to that.
Merge the tag bits into the old Xt value, as they should be.
Cc: qemu-stable@nongnu.org
Fixes: c15294c1e36a7dd9b25 ("target/arm: Implement LDG, STG, ST2G instructions")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate-a64.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 246e3c15145..4ec857bcd8d 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -4201,9 +4201,13 @@ static void disas_ldst_tag(DisasContext *s, uint32_t
insn)
if (s->ata) {
gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt);
} else {
+ /*
+ * Tag access disabled: we must check for aborts on the load
+ * load from [rn+offset], and then insert a 0 tag into rt.
+ */
clean_addr = clean_data_tbi(s, addr);
gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8);
- gen_address_with_allocation_tag0(tcg_rt, addr);
+ gen_address_with_allocation_tag0(tcg_rt, tcg_rt);
}
} else {
tcg_rt = cpu_reg_sp(s, rt);
--
2.34.1
- [PULL 00/33] target-arm queue, Peter Maydell, 2023/06/19
- [PULL 01/33] target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics, Peter Maydell, 2023/06/19
- [PULL 02/33] target/arm: Return correct result for LDG when ATA=0,
Peter Maydell <=
- [PULL 03/33] target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode, Peter Maydell, 2023/06/19
- [PULL 04/33] target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores, Peter Maydell, 2023/06/19
- [PULL 06/33] target/arm: Convert barrier insns to decodetree, Peter Maydell, 2023/06/19
- [PULL 07/33] target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree, Peter Maydell, 2023/06/19
- [PULL 12/33] target/arm: Convert LDXP, STXP, CASP, CAS to decodetree, Peter Maydell, 2023/06/19
- [PULL 13/33] target/arm: Convert load reg (literal) group to decodetree, Peter Maydell, 2023/06/19
- [PULL 05/33] target/arm: Convert hint instruction space to decodetree, Peter Maydell, 2023/06/19
- [PULL 09/33] target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree, Peter Maydell, 2023/06/19
- [PULL 11/33] target/arm: Convert load/store exclusive and ordered to decodetree, Peter Maydell, 2023/06/19
- [PULL 10/33] target/arm: Convert exception generation instructions to decodetree, Peter Maydell, 2023/06/19