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[PULL 12/20] target/tricore: Fix helper_ret() not correctly restoring PS
From: |
Bastian Koppelmann |
Subject: |
[PULL 12/20] target/tricore: Fix helper_ret() not correctly restoring PSW |
Date: |
Wed, 21 Jun 2023 18:14:14 +0200 |
We are always taking the TRICORE_FEATURE_13 branch as every CPU has
TRICORE_FEATURE_13.
For CPUs with ISA > 1.3 we have to take the else branch.
We fix this by inverting the condition. We check for
TRICORE_FEATURE_131, which every CPU except TRICORE_FEATURE_13 CPUs
have.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1700
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230612113245.56667-5-kbastian@mail.uni-paderborn.de>
---
target/tricore/op_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 9a7a26b171..821a4b67cb 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2584,12 +2584,12 @@ void helper_ret(CPUTriCoreState *env)
/* PCXI = new_PCXI; */
env->PCXI = new_PCXI;
- if (tricore_feature(env, TRICORE_FEATURE_13)) {
- /* PSW = new_PSW */
- psw_write(env, new_PSW);
- } else {
+ if (tricore_feature(env, TRICORE_FEATURE_131)) {
/* PSW = {new_PSW[31:26], PSW[25:24], new_PSW[23:0]}; */
psw_write(env, (new_PSW & ~(0x3000000)) + (psw & (0x3000000)));
+ } else { /* TRICORE_FEATURE_13 only */
+ /* PSW = new_PSW */
+ psw_write(env, new_PSW);
}
}
--
2.40.1
- [PULL 02/20] target/tricore: Add popcnt.w insn, (continued)
- [PULL 02/20] target/tricore: Add popcnt.w insn, Bastian Koppelmann, 2023/06/21
- [PULL 03/20] target/tricore: Add LHA insn, Bastian Koppelmann, 2023/06/21
- [PULL 04/20] target/tricore: Add crc32l.w insn, Bastian Koppelmann, 2023/06/21
- [PULL 05/20] target/tricore: Add crc32.b insn, Bastian Koppelmann, 2023/06/21
- [PULL 06/20] target/tricore: Add shuffle insn, Bastian Koppelmann, 2023/06/21
- [PULL 07/20] target/tricore: Implement SYCSCALL insn, Bastian Koppelmann, 2023/06/21
- [PULL 08/20] target/tricore: Add DISABLE insn variant, Bastian Koppelmann, 2023/06/21
- [PULL 09/20] target/tricore: Fix out-of-bounds index in imask instruction, Bastian Koppelmann, 2023/06/21
- [PULL 10/20] target/tricore: Correctly fix saving PSW.CDE to CSA on call, Bastian Koppelmann, 2023/06/21
- [PULL 11/20] target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs, Bastian Koppelmann, 2023/06/21
- [PULL 12/20] target/tricore: Fix helper_ret() not correctly restoring PSW,
Bastian Koppelmann <=
- [PULL 13/20] target/tricore: Fix RR_JLI clobbering reg A[11], Bastian Koppelmann, 2023/06/21
- [PULL 14/20] target/tricore: Introduce DISAS_TARGET_EXIT, Bastian Koppelmann, 2023/06/21
- [PULL 15/20] target/tricore: ENABLE exit to main-loop, Bastian Koppelmann, 2023/06/21
- [PULL 16/20] target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr(), Bastian Koppelmann, 2023/06/21
- [PULL 17/20] target/tricore: Introduce priv tb flag, Bastian Koppelmann, 2023/06/21
- [PULL 18/20] target/tricore: Implement privilege level for all insns, Bastian Koppelmann, 2023/06/21
- [PULL 19/20] target/tricore: Honour privilege changes on PSW write, Bastian Koppelmann, 2023/06/21
- [PULL 20/20] target/tricore: Fix ICR.IE offset in RESTORE insn, Bastian Koppelmann, 2023/06/21
- Re: [PULL 00/20] tricore queue, Richard Henderson, 2023/06/21