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Re: [PATCH v2 4/5] tests/qtest/hd-geo-test: fix test by removing unneces
From: |
Ani Sinha |
Subject: |
Re: [PATCH v2 4/5] tests/qtest/hd-geo-test: fix test by removing unnecessary pcie-root-port |
Date: |
Mon, 26 Jun 2023 17:01:29 +0530 |
> On 26-Jun-2023, at 4:45 PM, Igor Mammedov <imammedo@redhat.com> wrote:
>
> On Thu, 22 Jun 2023 16:02:54 +0530
> Ani Sinha <anisinha@redhat.com> wrote:
>
>> A SCSI controller can be attached to a pcie-to-pci bridge which in turn can
>> be
>> attached directly to the root bus (peie.0). There is no need to attach a
>> pcie-root-port on the root bus in order to attach the pcie-ro-pci bridge.
>> Fix it.
>
> bridge can be both on pcie.0 or on root-port and both are valid configs.
> So what exactly and why we are fixing here?
If you look at the functions carefully, “br” is a pcie-root-port and “pcie.0”
is a pcie-to-pci bridge.
The bug here is that both the SCSI controller and the pcie-to-pci bridge
(pcie.0) were getting attached to the same pcie-root-port. I think the
intention of the author was to attach the SCSI controller to pcie-to-pci bridge.
In any case, I do not see the reason to attach a pcie-root-port here. We can
attach the pcie-to-pci bridge on the RC and then attach the SCSI controllers on
the bridge.
>
>>
>> CC: mst@redhat.com
>> CC: imammedo@redhat.com
>> CC: Michael Labiuk <michael.labiuk@virtuozzo.com>
>>
>> Signed-off-by: Ani Sinha <anisinha@redhat.com>
>> ---
>> tests/qtest/hd-geo-test.c | 18 ++++++++----------
>> 1 file changed, 8 insertions(+), 10 deletions(-)
>>
>> diff --git a/tests/qtest/hd-geo-test.c b/tests/qtest/hd-geo-test.c
>> index 5aa258a2b3..d08bffad91 100644
>> --- a/tests/qtest/hd-geo-test.c
>> +++ b/tests/qtest/hd-geo-test.c
>> @@ -784,14 +784,12 @@ static void test_override_scsi(void)
>> test_override(args, "pc", expected);
>> }
>>
>> -static void setup_pci_bridge(TestArgs *args, const char *id, const char
>> *rootid)
>> +static void setup_pci_bridge(TestArgs *args, const char *id)
>> {
>>
>> - char *root, *br;
>> - root = g_strdup_printf("-device pcie-root-port,id=%s", rootid);
>> - br = g_strdup_printf("-device pcie-pci-bridge,bus=%s,id=%s", rootid,
>> id);
>> + char *br;
>> + br = g_strdup_printf("-device pcie-pci-bridge,bus=pcie.0,id=%s", id);
>>
>> - args->argc = append_arg(args->argc, args->argv, ARGV_SIZE, root);
>> args->argc = append_arg(args->argc, args->argv, ARGV_SIZE, br);
>> }
>>
>> @@ -811,8 +809,8 @@ static void test_override_scsi_q35(void)
>> add_drive_with_mbr(args, empty_mbr, 1);
>> add_drive_with_mbr(args, empty_mbr, 1);
>> add_drive_with_mbr(args, empty_mbr, 1);
>> - setup_pci_bridge(args, "pcie.0", "br");
>> - add_scsi_controller(args, "lsi53c895a", "br", 3);
>> + setup_pci_bridge(args, "pcie-pci-br");
>> + add_scsi_controller(args, "lsi53c895a", "pcie-pci-br", 3);
>> add_scsi_disk(args, 0, 0, 0, 0, 0, 10000, 120, 30);
>> add_scsi_disk(args, 1, 0, 0, 1, 0, 9000, 120, 30);
>> add_scsi_disk(args, 2, 0, 0, 2, 0, 1, 0, 0);
>> @@ -868,9 +866,9 @@ static void test_override_virtio_blk_q35(void)
>> };
>> add_drive_with_mbr(args, empty_mbr, 1);
>> add_drive_with_mbr(args, empty_mbr, 1);
>> - setup_pci_bridge(args, "pcie.0", "br");
>> - add_virtio_disk(args, 0, "br", 3, 10000, 120, 30);
>> - add_virtio_disk(args, 1, "br", 4, 9000, 120, 30);
>> + setup_pci_bridge(args, "pcie-pci-br");
>> + add_virtio_disk(args, 0, "pcie-pci-br", 3, 10000, 120, 30);
>> + add_virtio_disk(args, 1, "pcie-pci-br", 4, 9000, 120, 30);
>> test_override(args, "q35", expected);
>> }
>>
>
- [PATCH v2 0/5] test and QEMU fixes to ensure proper PCIE device usage, Ani Sinha, 2023/06/22
- [PATCH v2 1/5] tests/acpi: allow changes in DSDT.noacpihp table blob, Ani Sinha, 2023/06/22
- [PATCH v2 2/5] tests/acpi/bios-tables-test: use the correct slot on the pcie-root-port, Ani Sinha, 2023/06/22
- [PATCH v2 3/5] tests/acpi/bios-tables-test: update acpi blob q35/DSDT.noacpihp, Ani Sinha, 2023/06/22
- [PATCH v2 4/5] tests/qtest/hd-geo-test: fix test by removing unnecessary pcie-root-port, Ani Sinha, 2023/06/22
- [PATCH v2 5/5] hw/pci: ensure PCIE devices are plugged into only slot 0 of PCIE port, Ani Sinha, 2023/06/22