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[PULL 05/14] target/arm: Dump ZA[] when active
From: |
Peter Maydell |
Subject: |
[PULL 05/14] target/arm: Dump ZA[] when active |
Date: |
Thu, 6 Jul 2023 14:25:03 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Always print each matrix row whole, one per line, so that we
get the entire matrix in the proper shape.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230622151201.1578522-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f12c714bc43..adf84f96860 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1082,6 +1082,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE
*f, int flags)
i, q[1], q[0], (i & 1 ? "\n" : " "));
}
}
+
+ if (cpu_isar_feature(aa64_sme, cpu) &&
+ FIELD_EX64(env->svcr, SVCR, ZA) &&
+ sme_exception_el(env, el) == 0) {
+ int zcr_len = sve_vqm1_for_el_sm(env, el, true);
+ int svl = (zcr_len + 1) * 16;
+ int svl_lg10 = svl < 100 ? 2 : 3;
+
+ for (i = 0; i < svl; i++) {
+ qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i);
+ for (j = zcr_len; j >= 0; --j) {
+ qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c",
+ env->zarray[i].d[2 * j + 1],
+ env->zarray[i].d[2 * j],
+ j ? ':' : '\n');
+ }
+ }
+ }
}
#else
--
2.34.1
- [PULL v2 00/14] target-arm queue, Peter Maydell, 2023/07/06
- [PULL 02/14] hw/arm/sbsa-ref: use XHCI to replace EHCI, Peter Maydell, 2023/07/06
- [PULL 01/14] target/arm: Add raw_writes ops for register whose write induce TLB maintenance, Peter Maydell, 2023/07/06
- [PULL 08/14] tests/qtest: xlnx-canfd-test: Fix code coverity issues, Peter Maydell, 2023/07/06
- [PULL 13/14] target/arm: Define neoverse-v1, Peter Maydell, 2023/07/06
- [PULL 06/14] target/arm: Fix SME full tile indexing, Peter Maydell, 2023/07/06
- [PULL 10/14] hw: arm: allwinner-sramc: Set class_size, Peter Maydell, 2023/07/06
- [PULL 09/14] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG, Peter Maydell, 2023/07/06
- [PULL 12/14] target/arm: Suppress more TCG unimplemented features in ID registers, Peter Maydell, 2023/07/06
- [PULL 05/14] target/arm: Dump ZA[] when active,
Peter Maydell <=
- [PULL 07/14] target/arm: Handle IC IVAU to improve compatibility with JITs, Peter Maydell, 2023/07/06
- [PULL 03/14] tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and id_aa64smfr0_el1, Peter Maydell, 2023/07/06
- [PULL 11/14] target/xtensa: Assert that interrupt level is within bounds, Peter Maydell, 2023/07/06
- [PULL 04/14] target/arm: Avoid splitting Zregs across lines in dump, Peter Maydell, 2023/07/06
- [PULL 14/14] target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case, Peter Maydell, 2023/07/06
- Re: [PULL v2 00/14] target-arm queue, Richard Henderson, 2023/07/06