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[PULL 03/44] hw/mips/loongson3_virt: Relax CPU restrictions for TCG
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 03/44] hw/mips/loongson3_virt: Relax CPU restrictions for TCG |
Date: |
Tue, 11 Jul 2023 00:25:30 +0200 |
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
After implemented CPUCFG and CSR, we are now able to boot Linux
kernel with Loongson-3A4000 CPU, so there is no point to restrict
CPU type to 3A1000 only, instead we just check for presence of
INSN_LOONGSON3A.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20230521214832.20145-3-jiaxun.yang@flygoat.com>
[JY: Check for cpu_type_supports_isa(INSN_LOONGSON3A)]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/loongson3_virt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index 3dd91da7a6..4018b8c1d3 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -481,8 +481,8 @@ static void mips_loongson3_virt_init(MachineState *machine)
if (!machine->cpu_type) {
machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
}
- if (!strstr(machine->cpu_type, "Loongson-3A1000")) {
- error_report("Loongson-3/TCG needs cpu type Loongson-3A1000");
+ if (!cpu_type_supports_isa(machine->cpu_type, INSN_LOONGSON3A)) {
+ error_report("Loongson-3/TCG needs a Loongson-3 series cpu");
exit(1);
}
} else {
--
2.38.1
- [PULL 00/44] MIPS patches for 2023-07-10, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 01/44] target/mips: Rework cp0_timer with clock API, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 02/44] target/mips: Implement Loongson CSR instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 03/44] hw/mips/loongson3_virt: Relax CPU restrictions for TCG,
Philippe Mathieu-Daudé <=
- [PULL 04/44] target/mips: Add emulation of MXU instructions for 32-bit load/store, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 05/44] target/mips: Add support of two XBurst CPUs, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 06/44] target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 07/44] target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 08/44] target/mips/mxu: Add Q8SLT Q8SLTU instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 09/44] target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructions, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 10/44] target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 11/44] target/mips/mxu: Add Q8ADD instruction, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 12/44] target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insns, Philippe Mathieu-Daudé, 2023/07/10
- [PULL 13/44] target/mips/mxu: Add D16MULF D16MULE instructions, Philippe Mathieu-Daudé, 2023/07/10