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[PULL 46/63] hw/cxl: Add utility functions decoder interleave ways and t
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From: |
Michael S. Tsirkin |
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Subject: |
[PULL 46/63] hw/cxl: Add utility functions decoder interleave ways and target count. |
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Date: |
Wed, 4 Oct 2023 04:45:39 -0400 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
As an encoded version of these key configuration parameters is available
in a register, provide functions to extract it again so as to avoid
the need for duplicating the storage.
Whilst here update the _enc() function to include additional values
as defined in the CXL 3.0 specification. Whilst they are not
currently used in the emulation, they may be in future and it is
easier to compare with the specification if all values are covered.
Add a spec reference for cxl_interleave_ways_enc() for consistency
with the target count equivalent (and because it's nice to know where
the magic numbers come from).
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230913132523.29780-3-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/cxl/cxl_component.h | 2 ++
hw/cxl/cxl-component-utils.c | 60 ++++++++++++++++++++++++++++++----
2 files changed, 56 insertions(+), 6 deletions(-)
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index bdb3881a6b..ef9e033919 100644
--- a/include/hw/cxl/cxl_component.h
+++ b/include/hw/cxl/cxl_component.h
@@ -226,8 +226,10 @@ void cxl_component_create_dvsec(CXLComponentState
*cxl_cstate,
uint16_t type, uint8_t rev, uint8_t *body);
int cxl_decoder_count_enc(int count);
+int cxl_decoder_count_dec(int enc_cnt);
uint8_t cxl_interleave_ways_enc(int iw, Error **errp);
+int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp);
uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp);
hwaddr cxl_decode_ig(int ig);
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index ea2d4770ec..5f38f2016f 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -13,15 +13,45 @@
#include "hw/pci/pci.h"
#include "hw/cxl/cxl.h"
+/* CXL r3.0 Section 8.2.4.19.1 CXL HDM Decoder Capability Register */
int cxl_decoder_count_enc(int count)
{
switch (count) {
- case 1: return 0;
- case 2: return 1;
- case 4: return 2;
- case 6: return 3;
- case 8: return 4;
- case 10: return 5;
+ case 1: return 0x0;
+ case 2: return 0x1;
+ case 4: return 0x2;
+ case 6: return 0x3;
+ case 8: return 0x4;
+ case 10: return 0x5;
+ /* Switches and Host Bridges may have more than 10 decoders */
+ case 12: return 0x6;
+ case 14: return 0x7;
+ case 16: return 0x8;
+ case 20: return 0x9;
+ case 24: return 0xa;
+ case 28: return 0xb;
+ case 32: return 0xc;
+ }
+ return 0;
+}
+
+int cxl_decoder_count_dec(int enc_cnt)
+{
+ switch (enc_cnt) {
+ case 0x0: return 1;
+ case 0x1: return 2;
+ case 0x2: return 4;
+ case 0x3: return 6;
+ case 0x4: return 8;
+ case 0x5: return 10;
+ /* Switches and Host Bridges may have more than 10 decoders */
+ case 0x6: return 12;
+ case 0x7: return 14;
+ case 0x8: return 16;
+ case 0x9: return 20;
+ case 0xa: return 24;
+ case 0xb: return 28;
+ case 0xc: return 32;
}
return 0;
}
@@ -393,6 +423,7 @@ void cxl_component_create_dvsec(CXLComponentState *cxl,
cxl->dvsec_offset += length;
}
+/* CXL r3.0 Section 8.2.4.19.7 CXL HDM Decoder n Control Register */
uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
{
switch (iw) {
@@ -410,6 +441,23 @@ uint8_t cxl_interleave_ways_enc(int iw, Error **errp)
}
}
+int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp)
+{
+ switch (iw_enc) {
+ case 0x0: return 1;
+ case 0x1: return 2;
+ case 0x2: return 4;
+ case 0x3: return 8;
+ case 0x4: return 16;
+ case 0x8: return 3;
+ case 0x9: return 6;
+ case 0xa: return 12;
+ default:
+ error_setg(errp, "Encoded interleave ways: %d not supported", iw_enc);
+ return 0;
+ }
+}
+
uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp)
{
switch (gran) {
--
MST
- [PULL 51/63] vdpa net: stop probing if cannot set features, (continued)
- [PULL 51/63] vdpa net: stop probing if cannot set features, Michael S. Tsirkin, 2023/10/04
- [PULL 55/63] pcie_sriov: unregister_vfs(): fix error path, Michael S. Tsirkin, 2023/10/04
- [PULL 47/63] hw/cxl: Fix and use same calculation for HDM decoder block size everywhere, Michael S. Tsirkin, 2023/10/04
- [PULL 45/63] hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .c, Michael S. Tsirkin, 2023/10/04
- [PULL 60/63] util/uuid: add a hash function, Michael S. Tsirkin, 2023/10/04
- [PULL 53/63] amd_iommu: Fix APIC address check, Michael S. Tsirkin, 2023/10/04
- [PULL 56/63] libvhost-user.c: add assertion to vu_message_read_default, Michael S. Tsirkin, 2023/10/04
- [PULL 61/63] hw/display: introduce virtio-dmabuf, Michael S. Tsirkin, 2023/10/04
- [PULL 57/63] virtio: use shadow_avail_idx while checking number of heads, Michael S. Tsirkin, 2023/10/04
- [PULL 40/63] hw/i386/acpi-build: Determine SMI command port just once, Michael S. Tsirkin, 2023/10/04
- [PULL 46/63] hw/cxl: Add utility functions decoder interleave ways and target count.,
Michael S. Tsirkin <=
- [PULL 54/63] hw/i386/pc: improve physical address space bound check for 32-bit x86 systems, Michael S. Tsirkin, 2023/10/04
- [PULL 52/63] vdpa net: follow VirtIO initialization properly at cvq isolation probing, Michael S. Tsirkin, 2023/10/04
- [PULL 59/63] virtio: remove unused next argument from virtqueue_split_read_next_desc(), Michael S. Tsirkin, 2023/10/04
- [PULL 63/63] libvhost-user: handle shared_object msg, Michael S. Tsirkin, 2023/10/04
- [PULL 62/63] vhost-user: add shared_object msg, Michael S. Tsirkin, 2023/10/04
- [PULL 43/63] vdpa: fix gcc cvq_isolated uninitialized variable warning, Michael S. Tsirkin, 2023/10/04
- [PULL 58/63] virtio: remove unnecessary thread fence while reading next descriptor, Michael S. Tsirkin, 2023/10/04
- Re: [PULL 00/63] virtio,pci: features, cleanups, Philippe Mathieu-Daudé, 2023/10/04
- Re: [PULL 00/63] virtio,pci: features, cleanups, Michael S. Tsirkin, 2023/10/04